Abstract: A mechanism is provided by which a hardware accelerator detects migration of a software process among processors and uses this information to write operation results to an appropriate cache memory for faster access by the current processor. This mechanism is provided, in part, by incorporation within the hardware accelerator of a mapping table having entries including a cache memory identifier associated with a processor identifier. The hardware accelerator further includes circuitry configured to receive a processor identifier from a calling processor, and to perform a look-up in the mapping table to determine the cache memory identifier associated with the processor identifier. The hardware accelerator uses the associated cache memory identifier to write results of called operations to the cache memory associated with the calling processor, thereby accelerating subsequent operations by the calling processor that rely upon the hardware accelerator results.

Abstract: A semiconductor device includes a trench in a semiconductor material having a device section and a termination section. A gate structure is located in the trench. With some embodiments, the transverse cross-sectional width of the termination section is wider than the transverse cross-sectional width of the device section.

Abstract: A radar unit (100, 300) is described that comprises: a frequency generation circuit (103, 106, 303, 306) configured to generate a millimetre wave, mmW, frequency modulated continuous wave, FMCW, transmit signal comprising a plurality of chirps; a transmitter circuit (108, 102, 308, 302) configured to transmit the generated mmW FMCW transmit signal: a receiver circuit (104, 110, 304, 310) configured to receive an echo of the mmW FMCW transmit signal; and a built-in self-test, BIST, circuit (140, 340) coupled to the receiver circuit (104, 110, 304, 310) and configured to process the echo of the mmW FMCW transmit signal.

Abstract: A built-in self-test (BIST) block is provided that is incorporated into an all-digital phase locked loop (ADPLL) located on chip with the ADPLL. The BIST performs testing functions without need for support external to the chip. Test setup, test control, and test evaluation are performed entirely on chip. The BIST provides information regarding success or failure of the testing and can provide error information regarding test cases that do not pass successfully.

Abstract: An early fusion network is provided that reduces network load and enables easier design of specialized ASIC edge processors through performing a portion of convolutional neural network layers at distributed edge and data-network processors prior to transmitting data to a centralized processor for fully-connected/deconvolutional neural networking processing. Embodiments can provide convolution and downsampling layer processing in association with the digital signal processors associated with edge sensors. Once the raw data is reduced to smaller feature maps through the convolution-downsampling process, this reduced data is transmitted to a central processor for further processing such as regression, classification, and segmentation, along with feature combination of the data from the sensors.

Abstract: A system, method, and apparatus are provided for securely controlling operations of a data processing system in which security subsystem is activated to provide security services by responding to a security service request, evaluating the request against an adjustable set of system security policies to determine if the security service request is granted access to a protected asset, by generating a response to the security service request using the protected asset if the security service request is granted access to the protected asset, by adjusting a security access policy for the protected asset in the adjustable set of system security policies, and by sending the response from the security subsystem to the external application subsystem.

Abstract: A system, method, and apparatus are provided for securely controlling operations of a data processing system by activating a security subsystem to control startup behavior of application subsystems, installing SMR parameters which include an initial authenticity proof for use with an initial verification process for the SMR and calculating an alternate authenticity proof for use with a subsequent verification process for the SMR, and then by subsequently verifying the SMR using the alternate authenticity proof for the subsequent verification process applied to the SMR so that the security subsystem can apply a comprehensive system reaction for the application subsystem based on the SMR verification results.

Abstract: A mechanism for making multiple security schemes available in a single embedded system without requiring a firmware update or a hardware extension is provided. Embodiments provide firmware support for storing parameters related to each available security scheme and a selection mechanism to select the desired security scheme for the application utilizing the embedded system. Embodiments can also provide a status register to provide to a user an identification of the security scheme that is presently enabled on the embedded system. Embodiments can further prevent a malicious user from selecting an invalid security scheme.

Abstract: One example discloses a near-field wireless device, configured to be coupled to a host conductive structure, including: an electric near-field antenna, having a first conductive antenna surface coupled to a first feed point, and a second conductive antenna surface coupled to a second feed point; wherein the first and second conductive surfaces are separated by an air-gap; wherein the first and second conductive surfaces are configured to be substantially equidistant from the host conductive structure; and wherein the first and second conductive surfaces geometrically conform to the host conductive structure.

Abstract: A switched-capacitor amplifier circuit includes multiple switched-capacitor networks, an amplifier, and multiple reset circuits. The switched-capacitor networks are configured to receive respective input voltages during a sampling phase, and generate sampled voltages. During an amplification phase, the amplifier is coupled with the switched-capacitor networks, and is configured to receive the sampled voltages. The amplifier is further configured to generate output voltages. During the sampling phase, the amplifier is coupled with the reset circuits, and is further configured to receive divided voltages such that the amplifier is reset. The reset circuits are configured to receive and provide a common-mode voltage and the output voltages to the amplifier. The divided voltages are generated based on the common-mode voltage and the output voltages. Each reset circuit includes at least one of a resistor and a capacitor.

Abstract: Techniques for signaling new versions of a communication protocol differentiated from legacy versions of the communication protocol that are interoperable with stations implementing legacy versions of the communication protocol, that are compatible with future new versions of the communication protocol, and that do not overly complicate the receiver state machine have been disclosed.

Abstract: An electrostatic discharge (ESD) protection scheme is provided that reduces EMI noise propagation among functional circuit blocks of an integrated circuit (IC). Traditional ESD protection schemes include an ESD bus electrically tied to the substrate of an integrated circuit (e.g., a P-well) and substrate well regions associated with electromagnetic interference (EMI) aggressor and sensitive circuits. These electrical couplings can propagate EMI noise on the ESD bus throughout the circuit blocks of the IC. Embodiments provide an ESD bus that is not tied to the substrate well regions associated with EMI aggressor and sensitive circuits of the IC, but instead is a separate conductive layer electrically coupled to an external ground. In this manner, the device circuits are isolated from EMI noise carried in the ESD bus, thereby protecting the various functional blocks from such noise.

Abstract: A high bandwidth continuous time linear equalization (HBCTLE) circuit is disclosed. The HBCTLE circuit includes a continuous time linear equalization (CTLE) circuit and a gain circuit coupled with an output of the CTLE circuit. A feedback circuit is coupled between the output of the CTLE circuit and an output of the gain circuit.

Abstract: In accordance with a first aspect of the present disclosure, a radio frequency identification (RFID) transponder is provided, comprising a modulator, a current sensor and a clock recovery circuit, wherein: the modulator is configured to modulate an unmodulated carrier signal received from an external RFID reader; the current sensor is configured to sense a current that flows through one or more transistors comprised in the modulator; and the clock recovery circuit is configured to recover a clock signal using the current sensed by the current sensor. In accordance with a second aspect of the present disclosure, a corresponding method of operating a radio frequency identification (RFID) transponder is conceived.

Abstract: Various embodiments relate to a method of generating a shared secret for use in a symmetric cipher, including: receiving, by a processor, an encoded key Enc(K) and a white-box implementation of the symmetric cipher, where the encoded key Enc(K) is used in the white-box implementation; selecting, by the processor, homomorphic functions ? and ? and the values c1 and c3 such that Enc(K)?c1=Enc(K?c3); and transmitting, by the processor, ? and c3 to another device.

Abstract: A method is provided for multiplying two polynomials. In the method, first and second polynomials are evaluated at 2t inputs, where t is greater than or equal to one, and where each input is a fixed power of two 2l/(2t) multiplied with a different power of a primitive root of unity, thereby creating 2 times 2t integers, where l is an integer such that 2l is at least as large as the largest coefficient of the resulting product multiplying the first and second polynomials. The 2 times 2t integers are then multiplied pairwise, and a modular reduction is performed to get 2t integers. A linear combination of the 2t integers multiplied with primitive roots of unity is computed to get 2t integers whose limbs in the base 2l-bit representation correspond to coefficients of the product of the first and second polynomials. The method can be implemented on a processor designed for performing RSA and/or ECC type cryptographic operations.

Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a method for operating a communications network is disclosed. The method involves setting, at a first network node in the communications network, a register value that is indicative of a fault status associated with the first network node, the register value being set in a physical layer device of the first network node, receiving fault status information at an element in the communications network, the fault status information corresponding to the register value that is set in the physical layer device of the first network node, and determining, at the element in the communications network, a fault status of the communications network in response to the fault status information received at the element in the communications network.

Abstract: An adaptive equalizer and automatic gain controller is disclosed. The adaptive equalizer and automatic gain controller includes a programmable continuous time linear equalizer (CTLE). The CTLE includes a control port to receive a control signal to adjust a frequency response of the CTLE. The adaptive equalizer and automatic gain controller also includes a power comparator coupled with an output of the CTLE and a controller coupled with the power comparator and the control port and configured to generate the control signal for the CTLE based on the output of the power comparator. The power comparator is configured to compare power of a low frequency part and a high frequency part of an output signal of the CTLE.

Abstract: A semiconductor device and methods for making the same are disclosed. The device may include: a first transistor structure; a second transistor structure; a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising a doped layer over the substrate, a dielectric layer over the doped layer, and a conductive fill material over the dielectric layer; a first conductive contact from the first transistor structure to a first bit line; a second conductive contact from the second transistor to a non-volatile memory element; and a third conductive contact from the non-volatile memory element to a second bit line.

Abstract: Embodiments of communications devices and methods for operating a communications device are described. In an embodiment, a communications device includes a complex multiplier configured to multiply a first input complex signal with a second input complex signal to generate an output complex signal, an amplifier configured to amplify an imaginary part of the output complex signal to generate an amplification result, a delay element configured to delay a rotation angle signal that is related to the second input complex signal, and a subtractor configured to subtract the amplification result from the delayed rotation angle signal to generate the rotation angle signal. Other embodiments are also described.