Patents Assigned to Renesas Electronics Corporation
  • Patent number: 10659722
    Abstract: A video signal receiving apparatus receives a first and second video signals for transmitting a same video content. When determining a size adjustment amount of a second video included in the second video signal, the video signal receiving apparatus performs scaling processing on a second image included in the second video signal to generate a scaling image and performs shift processing on the second image to generate a shift image. The video signal receiving apparatus calculates a similarity degree between a first image included in the first video signal and the scaling image, calculates a similarity degree between the first image and the shift image, and uses the scaling image or the shift image having the higher calculated similarity degree as an image to be subjected to the next scaling processing and the next shift processing.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichi Takagi, Ren Imaoka
  • Patent number: 10659026
    Abstract: A semiconductor device that can perform voltage monitoring with a small circuit area is provided. The resistive subdivision circuit RDIV performs the resistive subdivision of the input voltage Vin by means of the input ladder resistor (R1-R4), and drives the nMOS transistors MN1-MN3 by the subdivided input voltages Vi1-Vi3 each having different resistive subdivision ratios, respectively. The pMOS transistor MP0 is provided in common for the pMOS transistors MP1-MP3, and configures a current mirror circuit with each of the pMOS transistors MP1-MP3. The bias current generating circuit IBSG supplies a bias current to the pMOS transistor MP1.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masataka Minami
  • Patent number: 10658031
    Abstract: To provide a semiconductor memory device capable of storing multi-value data while suppressing an increase in the threshold voltage set for a memory cell. A semiconductor memory device according to an embodiment includes a plurality of memory cell pairs, each having a first memory cell and a second memory cell. The first memory cell is configured so as to set at least one threshold voltage, whereas the second memory cell is configured so as to set a plurality of threshold voltages. Data stored in the memory cell pairs is defined using differences between the threshold voltages of the second memory cell and the threshold voltage of the first memory cell.
    Type: Grant
    Filed: August 25, 2018
    Date of Patent: May 19, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Hirokazu Nagase
  • Patent number: 10658469
    Abstract: In a semiconductor device (MISFET) having a gate electrode formed over a nitride semiconductor layer with a gate insulating film interposed therebetween, the gate insulating film includes a first gate insulating film (oxide film of first metal) formed on the nitride semiconductor layer and a second gate insulating film (oxide film of second metal). The second metal (for example, Hf) has electronegativity lower than that of the first metal (for example, Al). Since the electronegativity of the second metal is lower than that of the first metal, negative charge is introduced into the oxide film of the first metal due to interfacial polarization, so that the flat-band voltage can be shifted in a positive direction. Accordingly, the threshold voltage which has become negative due to the heat treatment of the oxide film of the first metal can be shifted in the positive direction.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshihiro Iizuka, Shin Koyama, Yoshitake Kato
  • Patent number: 10656442
    Abstract: In an optical waveguide supplied with electricity by using a heater, miniaturization of the device is achieved by enhancing heat dissipation efficiency and heat resistance. In a modulator including an optical waveguide formed on an insulating film, a first interlayer insulating film that covers the optical waveguide, a heater formed on the first interlayer insulating film, and a second interlayer insulating film that covers the heater, a heat conducting portion adjacent to the optical waveguide and the heater and penetrating the first and second interlayer insulating films is formed.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: May 19, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Iida, Yasutaka Nakashiba, Shinichi Kuwabara
  • Patent number: 10658947
    Abstract: The junction temperature of a field effect transistor is detected with a higher degree of accuracy than in the past. A semiconductor device controls multiple field effect transistors that configure a power conversion device, and includes a differential amplifier and a controller that controls ON/OFF of the multiple field effect transistors. The differential amplifier detects the potential difference between a source and a drain of a field effect transistor that is controlled in the OFF state by the controller and that induces an electric current flowing through the body diode thereof, among the multiple field effect transistors.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Satoshi Narumi
  • Patent number: 10654427
    Abstract: A semiconductor device for controlling an apparatus includes a first memory that stores data indicating, in association with each other, a factor that occurs with respect to the apparatus and control contents of the apparatus to be performed with respect to the factor; a second memory, and a processor executing program instructions and configured to estimate the factor and a required time until encountering the factor based on a result of an observation of a periphery of the apparatus, and decide control contents of the apparatus based on the estimated factor and the data, to control the apparatus. The first memory stores data which a required time until encountering the factor is greater than a threshold, and the second memory stores data which a required time until encountering the factor is equal to or less than the threshold.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: May 19, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuki Kajiwara
  • Patent number: 10651301
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having an upper surface, a trench electrode placed inside a trench formed on the upper surface, and a trench insulating film placed between the trench electrode and the semiconductor substrate, and the semiconductor substrate includes a drift layer, a floating layer for electric field reduction, a hole barrier layer, a body layer and an emitter layer, and the emitter layer, the body layer and the hole barrier layer are separated from the drift layer by the floating layer for electric field reduction, and a path of a carrier passing through an inverted layer formed in the body layer includes the body layer, the hole barrier layer, a non-inverted region of the floating layer for electric field reduction, and the drift layer.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: May 12, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Ryo Kanda, Hitoshi Matsuura
  • Patent number: 10651277
    Abstract: In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 12, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yuya Abiko, Natsuo Yamaguchi, Satoshi Eguchi
  • Patent number: 10651094
    Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 12, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideki Aono, Tetsuya Yoshida, Makoto Ogasawara, Shinichi Okamoto
  • Patent number: 10651188
    Abstract: In a MONOS memory having an ONO film, dielectric breakdown and a short circuit are prevented from occurring between the end of the lower surface of a control gate electrode over the ONO film and a semiconductor substrate under the ONO film. When a polysilicon film formed over the ONO film ON is processed to form the control gate electrode, the ONO film is not processed. Subsequently, a second offset spacer covering the side surface of the control gate electrode is formed. Then, using the second offset spacer as a mask, the ONO film is processed. This results in a shape in which in the gate length direction of the control gate electrode, the ends of the ONO film protrude outwardly from the side surfaces of the control gate electrode, respectively.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: May 12, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Hideaki Yamakoshi, Takashi Hashimoto, Shinichiro Abe, Yuto Omizu
  • Patent number: 10649830
    Abstract: It is determined whether an arithmetic operation function of a device to be inspected is normal or not. A MCU 13 to be inspected acquires a constant to be used for an arithmetic problem from a power source IC 12 on an inspection side. The MCU 13 sequentially selects a plurality of the arithmetic problems and carries out an arithmetic operation using the acquired constant according to the selected arithmetic problem. A monitoring circuit 23 of the power source IC 12 receives the result of the arithmetic operation of the arithmetic problem from the MCU 13. The monitoring circuit 23 compares the received arithmetic operation result with the arithmetic operation result of the arithmetic problem calculated at the side of the monitoring circuit 23. The monitoring circuit 23 determines whether the arithmetic operation function of the MCU 13 works normally or not based on the comparison result.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: May 12, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Seiichi Kousokabe
  • Patent number: 10650883
    Abstract: In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: May 12, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Yamaki
  • Patent number: 10650949
    Abstract: A semiconductor device capable of reducing in size thereof and suppressing degradation in the characteristics of circuit components is provided. The semiconductor device includes an LC circuit comprised of a spiral inductor provided over a semiconductor substrate and a capacitive element coupled with the spiral inductor. The spiral inductor includes a central area encircled with a metal wiring and a peripheral area other than the central area. The capacitive element is formed in an upper-layer or a lower-layer position corresponding to the peripheral area other than the central area.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: May 12, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hironori Asano, Noriaki Matsuno
  • Patent number: 10649034
    Abstract: A battery voltage monitoring apparatus monitoring a voltage of an assembled battery, the assembled battery including a plurality of battery cells, comprising; a first voltage sensor module that monitors voltages of a plurality of battery cells arranged at a high voltage side; and a second voltage sensor module that monitors voltages of a plurality of battery cells arranged at a low voltage side, wherein the second voltage sensor module comprises a voltage sensor that is connected to a terminal and detects a voltage of a battery cell connected to the terminal, the terminal being supplied with a power source potential of the second voltage sensor module, the voltage sensor comprises a comparator including a first terminal and a second terminal, the first terminal being supplied with a voltage according to the voltage of the battery cell, the second terminal being supplied with a reference voltage.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: May 12, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Manabu Miyamoto
  • Patent number: 10642768
    Abstract: In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced. The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masaru Hase, Tetsuji Tsuda, Naohiro Nishikawa, Yuki Inoue, Seiji Mochizuki, Katsushige Matsubara, Ren Imaoka
  • Patent number: 10644580
    Abstract: A power supply circuit capable of generating a stable output voltage is provided. According to one embodiment, the power supply circuit includes a comparison unit that compares the divided voltage corresponding to the external output voltage with each of the first reference voltage and the second reference voltage to output the comparison result, a NAND circuit that controls whether or not to output the clock signal based on the comparison result by the comparison unit, and a booster circuit that boosts the external output voltage when the clock signal is supplied via the NAND circuit.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kenichi Nagamatsu
  • Patent number: 10642607
    Abstract: A determination apparatus includes a difference code generation section that generates a first difference code and a second difference code, the first difference code representing a set of code pieces in a first program that are different from code pieces in a second program, the second difference code representing a set of code pieces in the second program that are different from code pieces in the first program, a logical expression derivation section that performs predetermined conversion to derive a first logical expression from the first difference code and derive a second logical expression from the second difference code, and a determination section that, depending on whether the second logical expression includes the first logical expression, determines whether the first program in a predetermined embedded device is dynamically updatable to the second program.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tadaaki Tanimoto, Naoyuki Morita
  • Patent number: 10644679
    Abstract: A level shift circuit includes a pulse signal generation unit generating first and second pulse signals with respect to an input signal, a first level conversion unit converting the first pulse signal at a first voltage to a third pulse signal at a second voltage, a second level conversion unit converting the second pulse signal at the first voltage to a fourth pulse signal at the second voltage, and a flip flop circuit making an output signal at the second voltage rise according to the third pulse signal, and making the output signal at the second voltage fall according to the fourth pulse signal. The pulse signal generation unit compares the input signal with the output signal of the flip flop circuit, and generates the first pulse signal when the input signal rises and the second pulse signal when the input signal falls, based on a non-matching comparison result.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koichi Takeda
  • Patent number: 10643930
    Abstract: An improvement is achieved in the reliability of a semiconductor device. A SIP includes an analog chip, a microcomputer chip having a main surface smaller in area than a main surface of the analog chip, a die pad over which the analog chip and the microcomputer chip are mounted, and a plurality of leads arranged so as to surround the die pad. The SIP further includes a plurality of suspension leads formed integrally with the die pad, a plurality of wires electrically coupling electrodes of the analog chip to the leads and electrically coupling the microcomputer chip to the leads, and a sealing body sealing therein the analog chip and the microcomputer chip. Each of first and second curved portions of the die pad has a radius of curvature larger than a radius of curvature of a third curved portion of the die pad.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tadatoshi Danno, Atsushi Nishikizawa, Hiroyuki Nakamura