Abstract: A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section.

Abstract: A semiconductor device has a resistance change element that is high in the holding resistance of a low resistance (On) state while securing a memory window. In a resistance random access memory including selection transistors and resistance change elements coupled in series to the selection transistors, the resistance change element uses a lower electrode that applies a positive voltage when being transited to a high resistance (Off) state, an upper electrode that faces the lower electrode, and a resistance change layer that is sandwiched between the lower electrode and the upper electrode and that uses an oxide of transition metal. The resistance change layer contains nitrogen. The concentration of nitrogen on the lower electrode side is higher than that on the upper electrode side. The nitrogen in the resistance change layer exhibits a concentration gradient continuously declined from the lower electrode side to the upper electrode side.

Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Abstract: A sophisticated semiconductor device is provided. A semiconductor device including an IPD chip and an MCU chip which are included in one package. The IPD chip includes: a power transistor that drives an external load; a gate drive circuit that drives the power transistor; and a protection circuit that protects the power transistor from having a breakdown. The MCU chip includes an arithmetic processing unit that performs arithmetic processing based on detected data output from the protection circuit, and a storage unit that stores a program for the arithmetic processing unit. The MCU chip has a function of controlling operation of the power transistor according to the detected data.

Abstract: Performance of a semiconductor device is improved. Graphene particles are mixedly added in a sealing resin covering a semiconductor chip. The graphene particles are thus mixedly added in the sealing resin, thereby thermal conduction of the sealing resin is improved, and thus radiation performance of the semiconductor device can be improved. Graphene is a sheet of sp2 bonded carbon atoms having a monolayer thickness. Graphene has a structure where hexagonal lattices, each of which is formed of carbon atoms and bonds of the carbon atoms, are planarly spread. Graphene is preferably used as heat transfer filler because of its high thermal conductivity and light weight.

Abstract: An object of the invention is to improve precision of current detection in a switching system having plural switching circuits. A first PWM timing generation circuit generates an edge timing of a PWM signal by using a comparison value and a count value and drives a first switching circuit. A second PWM timing generation circuit generates an edge timing of a PWM signal of plural phases by using a comparison value and a count value and drives a second switching circuit. One of the switching circuits is an inverter circuit of a common shunt type in which a shunt resistor is provided commonly for plural phases. One of the PWM timing generation circuits shifts the generated edge timing so that an interval between an edge timing of one of the circuits and an AD conversion timing of the other becomes equal to or larger than a predetermined reference value.

Abstract: An electronic device has a power semiconductor device, a first semiconductor integrated circuit device, and a second semiconductor integrated circuit device. The power semiconductor device has a terminal outputting sense current. The first semiconductor integrated circuit device has an overcurrent detection circuit detecting overcurrent on the basis of the sense current, and a temperature detection circuit detecting temperature of the power semiconductor device. The second semiconductor integrated circuit device has a storage device storing a temperature characteristic of a current mirror ratio of the power semiconductor device, a temperature detecting unit calculating temperature on the basis of an output of the temperature detection circuit, and an overcurrent detection control unit controlling the overcurrent detection circuit on the basis of the temperature detected by the temperature detecting unit and the temperature characteristic of the current mirror ratio stored in the storage device.

Abstract: An improvement is achieved in the IE effect of a semiconductor device including an IGBT having an active cell region with an EGE structure. Each of a plurality of hybrid cell regions extending in a Y-axis direction has first, second, and third trench electrodes extending in the Y-axis direction, a p-type body region, and contact trenches provided between the first and second trench electrodes and between the first and third trench electrodes to extend in the Y-axis direction and reach middle points in the p-type body region. Each of the hybrid cell regions further has a plurality of n+-type emitter regions formed in an upper surface of a semiconductor substrate located between the contact trenches and the first trench electrode to be shallower than the contact trenches and spaced apart at regular intervals in the Y-direction in plan view. The n+-type emitter regions are arranged in a staggered configuration in plan view.

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes a buffer layer composed of a first nitride semiconductor layer, a channel layer composed of a second nitride semiconductor layer, and a barrier layer composed of a third nitride semiconductor layer, which are sequentially laminated, and a cap layer composed of a fourth nitride semiconductor layer of mesa type, which is formed over the barrier layer. The semiconductor device also includes a source electrode formed on one side of the cap layer, a drain electrode formed on the other side of the cap layer, and a first gate electrode formed over the cap layer. The first gate electrode and the cap layer are Schottky-joined. A Schottky gate electrode (the first gate electrode) is provided over the cap layer in this way, so that when a gate voltage is applied, an electric field is applied to the entire cap layer and a depletion layer spreads. Therefore, it is possible to suppress a gate leakage current.

Abstract: A method of manufacturing a semiconductor device includes a step of: patterning a conductive film formed over an interlayer insulating film so as to form a coil and a conductive pattern in the same layer, and then forming unevennesses on a surface of the interlayer insulating film by etching a portion of the interlayer insulating film with using the coil and the conductive pattern as a mask.

Abstract: To improve the performance of a semiconductor device, the semiconductor device includes an insulating film portion over a semiconductor substrate. The insulating film portion includes an insulating film containing silicon and oxygen, a first charge storage film containing silicon and nitrogen, an insulating film containing silicon and oxygen, a second charge storage film containing silicon and nitrogen, and an insulating film containing silicon and oxygen. The first charge storage film is included by two charge storage films.

Abstract: A semiconductor device and a method of manufacturing the same are provided so as to suppress an increase in the forward voltage of a first diode even if a driving signal is inputted to the gate electrode of an insulating gate bipolar transistor. An IGBT has a p-type body region. An anode region of the first diode has the same impurity region as the p-type body region of the IGBT. An anode region of a second diode is surrounded by an emitter groove and thus the anode region is separated from the p-type body region of the IGBT by the emitter groove.

Abstract: A semiconductor device according to the present invention includes a plurality of masters (100), a memory controller (400a), a bus that connects the plurality of masters (100) and the memory controller (400a), a QoS information register (610) that stores QoS information of the plurality of masters (100), a right grant number controller (602) that calculates the number of grantable access rights based on space information of a buffer (401) of the memory controller (400a), a right grant selection controller (603a) that selects the master (100) which will be granted the access right based on the QoS information of the QoS information register (610) and the number of grantable rights from the right grant number controller (602), and a request issuing controller (201a) that does not pass a request of the master (100) which has not been granted the access right from the right grant selection controller (603a).

Abstract: A semiconductor device includes a variable current generating unit that sends a direct current of a value according to a control signal from one measurement node of a bridge circuit in which a change amount of a resistance value of a pressure-sensitive resistance element appears as a potential difference between measurement nodes, a potential difference determining unit that determines whether or not the potential difference has been generated, and a control unit that outputs the control signal to the variable current generating unit so that the variable current generating unit sends the direct current of a value that does not generate the potential difference based on a determination result of the potential difference determining unit.

Abstract: The present invention is directed to improve reliability of a semiconductor device. A semiconductor device manufacturing method includes: (a) a step of attaching a BGA having a solder ball to a socket for a burn-in test; and (b) a step of performing a burn-in test of the BGA by sandwiching the solder ball by conductive contact pins in the socket. The contact pin in the socket has a first projection part which is conductive and extends along an attachment direction of the BGA and a second projection part which is conductive, provided along a direction crossing the extension direction of the first projection part, and placed so as to face the surface on the attachment side of the BGA of the solder ball. In the step (b), a burn-in test of the BGA is performed in a state where the first projection parts in the contact pins are in contact with the solder ball.

Abstract: A storage device includes a plurality of flash memory cells, a controller which writes data into a memory cell which is used as the cell which stores data therein in the plurality of flash memory cells and performs resetting of a threshold voltage of a timer cell used for decision of a threshold voltage of the memory cell in the plurality of flash memory cells and a level decision unit which estimates a state of a second threshold voltage which is the current threshold voltage of the memory cell on the basis of a first threshold voltage which is the current threshold voltage of the timer cell.

Abstract: A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.

Abstract: A microcomputer includes a plurality of functional blocks that exchange information with each other. A nonvolatile memory can rewrite information stored therein and first data has been written therein in advance. A central processing unit processes information read from the nonvolatile memory or writes information to the nonvolatile memory. An abnormality detecting unit detects an abnormality in exchange of data between the plurality of functional blocks. A nonvolatile memory checking unit reads the first data from the nonvolatile memory when the abnormality detecting unit has detected an abnormality, compares the first data with second data indicating the content of the first data when written to the nonvolatile memory, and detects an abnormality in the nonvolatile memory when a result of the comparison shows that the first data is not identical to the second data.

Abstract: Miniaturization of a semiconductor device is attained. An SOP1 includes: a semiconductor chip; another semiconductor chip; a die pad over which the former semiconductor chip is mounted; another die pad over which the latter semiconductor chip is mounted; a plurality of wires; and a sealing body. In plan view of the SOP1, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad. Also, in a horizontal direction in cross sectional view, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad.

Abstract: Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.