Patents Assigned to RENESAS
  • Publication number: 20130055188
    Abstract: A semiconductor device for layout has first and second power supply domains and has wiring connected to and from cells belonging to a second power supply domain. A wiring inhibited/allowed area setting unit sets an exclusive wiring inhibited area and a pass-through wiring allowed area within the first power supply domain based on a repeater wire maximum length being a maximum wire length which a repeater buffer can drive. A wiring setting unit modifies wiring based on the exclusive wiring inhibited area and the pass-through wiring allowed area. A repeater insertion unit sets a repeater buffer to be inserted on a wire according to the repeater wire maximum length. The exclusive wiring inhibited area allows wiring connecting cells within the first power supply domain and inhibits pass-through wiring. The pass-through wiring allowed area, being the first power supply domain excluding the exclusive wiring inhibited area, allows pass-through wiring.
    Type: Application
    Filed: August 23, 2012
    Publication date: February 28, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideaki FUTAKATA
  • Publication number: 20130053092
    Abstract: Methods and apparatus are provided from the context of a mobile terminal and a target base station for creating neighbor measurement reports in accordance with a measure of mobility that takes into account whether a handover is mobility-triggered without consideration of non-mobility-triggered handovers. In this regard, a method is provided that includes receiving information indicating whether a handover is mobility triggered. The method may also determine, with a processor, a measure of mobility at least partially based upon the handovers that are mobility triggered without consideration of non-mobility triggered handovers. The method may also cause neighbor measurement reports to be provided in accordance with the measure of mobility.
    Type: Application
    Filed: August 23, 2011
    Publication date: February 28, 2013
    Applicant: RENESAS MOBILE CORPORATION
    Inventors: Pasi Petteri Laitinen, Antti-Eemeli Suronen, Antti Olavi Kangas
  • Publication number: 20130055040
    Abstract: An output control scan flip-flop according to the present invention includes a first scan flip-flop that captures first data in a first mode and second data in a second mode in synchronization with a clock signal to output the data that is captured, a second scan flip-flop that captures the data output from the first scan flip-flop in the second mode in synchronization with a clock signal to output the data that is captured, and a gating circuit that generates the data output from the first scan flip-flop in the first mode as output data, and generates output data having a change rate of a logic value lower than a change rate of a logic value of the data output from the first scan flip-flop based on the data output from each of the first scan flip-flop and the second scan flip-flop in the second mode.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 28, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Hayato KIMURA
  • Publication number: 20130052801
    Abstract: A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS AMERICA, INC., GLOBALFOUNDRIES, STMICROELECTRONICS, INC.
    Inventors: Nathaniel C. Berliner, Pranita Kulkarni, Nicolas Loubet, Kingsuk Maitra, Sanjay C. Mehta, Paul A. Ronsheim, Toyoji Yamamoto, Zhengmao Zhu
  • Publication number: 20130054956
    Abstract: A semiconductor device correctly switches endian modes regardless of the current endian mode of an interface. The semiconductor device includes a switching circuit and a first register. The switching circuit switches an interface tote used in big endian or little endian mode. The first register holds control, data of the switching circuit. The switching circuit sets the interface in little endian mode when first predetermined control information is supplied to the first register, and sets the interface in big endian mode when second predetermined control information is supplied to the first register. The control information can be correctly inputted without being influenced by the endian setting status.
    Type: Application
    Filed: October 28, 2012
    Publication date: February 28, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Renesas Electronics Corporation
  • Publication number: 20130049134
    Abstract: In a semiconductor device and a method of making the same, a first transistor has a gate stack comprising an underlying layer formed of a first material and an overlying layer formed of a second material. A second transistor has a gate stack comprising an underlying layer formed of a third material and an overlying layer formed of the second material. A third transistor has a gate stack comprising an underlying layer formed of the first material and an overlying layer formed of a fourth material. A fourth transistor has a gate stack comprising an underlying layer formed of the third material and an overlying material formed of the fourth material. Each of the first through fourth materials has a respectively different work function, so that each of the first through fourth transistors has a respectively different threshold voltage.
    Type: Application
    Filed: July 9, 2012
    Publication date: February 28, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroshi SUNAMURA
  • Publication number: 20130053037
    Abstract: Solving dual errors for user equipment UE checking whether a private cell is allowed when handing over between serving and target cells, where the PLMN and/or EPLMNs list of the serving and target cells may differ. The serving cell may send a one-bit indication that there is a change in a handover command or system information SI6 message after which the UE may or may not refrain from reporting new cells until it performs a registration/location area update in the target cell. The target cell may trigger in the UE a registration update then provide the UE with the PLMN of the target cell. The serving cell can provide the PLMN of the target cell in a SI6 message or handover command, which the UE may use in place of or in addition to the PLMN/EPLMN of the serving cell when checking whether a private/closed subscriber group cell is allowed.
    Type: Application
    Filed: July 20, 2012
    Publication date: February 28, 2013
    Applicant: RENESAS MOBILE CORPORATION
    Inventors: Harri A. JOKINEN, Guillaume SEBIRE, Vlora REXHEPI-VAN DER POL
  • Publication number: 20130051110
    Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.
    Type: Application
    Filed: August 30, 2012
    Publication date: February 28, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshihiko FUNAKI, Toshiharu OKAMOTO, Muneaki MATSUSHIGE, Kenichi KUBOYAMA, Shuuichi SENOU, Susumu TAKANO
  • Publication number: 20130045741
    Abstract: A method, apparatus and computer program product are provided in order to trigger a reselection of a serving cell in an instance in which a mobile terminal may be creating neighbor cell interference. Based upon received reselection data, the mobile terminal may release and/or suspend a network resource, such as an enhanced dedicated channel in order to trigger a reselection of a new serving cell. In this regard, a method is provided that includes determining the presence of a reselection condition based on reselection data. In an instance in which the presence of the reselection condition is determined, the method includes causing a network resource to be modified. The method also includes causing a reselection of a serving cell.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Applicant: RENESAS MOBILE CORPORATION
    Inventors: Brian Martin, Keiichi Kubota, Tao Chen
  • Publication number: 20130044530
    Abstract: A semiconductor memory device includes a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, an address pad column formed outside the memory cell array, the address pad column comprising a plurality of address pads that are arranged to be substantially parallel to the subarray columns, a data I/O pad column formed in a middle section of the memory cell array, the data I/O pad column comprising data I/O pads that are arranged to be substantially parallel to the subarray columns, an address input circuit arranged in the middle section of the memory cell array, and a pad input address line formed in a direction substantially perpendicular to the subarray columns on the memory cell array, the pad input address line directly connecting the address pad and the address input circuit.
    Type: Application
    Filed: October 23, 2012
    Publication date: February 21, 2013
    Applicants: RENESAS ELECTRONICS CORPORATION, NEC ELECTRONICS CORPORATION
    Inventors: NEC ELECTRONICS CORPORATION, RENESAS ELECTRONICS CORPORATION
  • Publication number: 20130043948
    Abstract: A semiconductor device for transmitting-signal amplification which has a fine resolution, a high dynamic range, a small occupied area, and low power consumption, is realized. An input signal amplitude is reduced every one half by a ladder network, and a transconductance amplifier stage is arranged corresponding to each node of the ladder network. An output of the transconductance amplifier stage is coupled to an output signal line in common. According to a control word WC<21:0>, the transconductance amplifier stage is enabled selectively, and the output current which appears in the output signal line is added.
    Type: Application
    Filed: October 19, 2012
    Publication date: February 21, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: RENESAS ELECTRONICS CORPORATION
  • Publication number: 20130045771
    Abstract: A method and apparatus are provided to reduce interference in neighbor cells by limiting the uplink power of an interfering mobile terminal In this regard, a method is provided that includes generating a measurement report, wherein the measurement report includes interference measurement information measured from at least one neighbor cell. The method also includes causing the generated measurement report to be transmitted to a receiving station. The method may also include receiving a power level indication from the receiving station, wherein the indication causes a modification of transmission power.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Applicant: RENESAS MOBILE CORPORATION
    Inventors: Brian Martin, Keiichi Kubota, Tao Chen
  • Publication number: 20130043576
    Abstract: To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP1, power MOSFETs Q1 and Q2 for the switch, a diode DD1 for detecting the heat generation of the power MOSFET Q1, a diode DD2 for detecting the heat generation of the power MOSFET Q2, and plural pad electrodes PD are formed. The power MOSFET Q1 and the diode DD1 are arranged in a first MOSFET region RG1 on the side of a side SD1, and the power MOSFET Q2 and the diode DD2 are arranged in a second MOSFET region RG2 on the side of a side SD2. The diode DD1 is arranged along the side SD1, the diode DD2 is arranged along the side SD2, and all pad electrodes PD other than the pad electrodes PDS1 and PDS2 for the source are arranged along a side SD3 between the diodes DD1 and DD2.
    Type: Application
    Filed: October 19, 2012
    Publication date: February 21, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Renesas Electronics Corporation
  • Publication number: 20130045693
    Abstract: A method, apparatus and computer program product are provided for triggering a measurement report from a mobile terminal, such as a mobile terminal is in the CELL_FACH state, to a network entity in an instance in which the mobile terminal may be creating neighbor cell interference. Based upon the measurement report, the serving cell may modify the operation of the mobile terminal in order to reduce the potential for neighbor cell interference. In this regard, a method is provided that includes determining two or more parameters indicative of neighbor cell interference. In instance in which the parameters satisfy respective thresholds, the method also causes a measurement report including an indication of at least one of the parameters to be provided to a network element.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Applicant: RENESAS MOBILE CORPORATION
    Inventors: Tao Chen, Keiichi Kubota, Brian Martin
  • Publication number: 20130037852
    Abstract: Super-junction MOSFETs by trench fill system requires void-free filling epitaxial growth. This may require alignment of plane orientations of trenches in a given direction. Particularly, when column layout at chip corner part is bilaterally asymmetrical with a diagonal line between chip corners, equipotential lines in a blocking state are curved at corner parts due to column asymmetry at chip corner. This tends to cause points where equipotential lines become dense, which may cause breakdown voltage reduction. In the present invention, in power type semiconductor active elements such as power MOSFETs, a ring-shaped field plate is disposed in chip peripheral regions around an active cell region, etc., assuming a nearly rectangular shape. The field plate has an ohmic-contact part in at least a part of the portion along the side of the rectangle. However, in the portion corresponding to the corner part of the rectangle, an ohmic-contact part is not disposed.
    Type: Application
    Filed: July 13, 2012
    Publication date: February 14, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Tomohiro TAMAKI
  • Publication number: 20130037947
    Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.
    Type: Application
    Filed: October 10, 2012
    Publication date: February 14, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Renesas Electronics Corporation
  • Publication number: 20130037795
    Abstract: An element using a semiconductor layer is formed between wiring layers and, at the same time, a gate electrode is formed using a conductive material other than a material for wirings. A first wiring is embedded in a surface of a first wiring layer. A gate electrode is formed over the first wiring. The gate electrode is coupled to the first wiring. The gate electrode is formed by a process different from a process for the first wiring. Therefore, the gate electrode can be formed using a material other than a material for the first wiring. Further, a gate insulating film and a semiconductor layer are formed over the gate electrode.
    Type: Application
    Filed: July 18, 2012
    Publication date: February 14, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroshi SUNAMURA, Naoya INOUE, Kishou KANEKO
  • Publication number: 20130039122
    Abstract: A magnetoresistive random access memory includes a memory cell line in which memory cells are formed and write bit lines. The memory cell line 1 includes a magnetic recording layer, magnetization fixed layers, reference layers, spacer layers, and nMOS transistors. The spacer layer and the reference layer are located between the magnetization fixed layer and the magnetization fixed layer). The magnetization fixed layers have a magnetization fixed to a direction opposite to that of a magnetization of the magnetization fixed layers. The reference layers also have a fixed magnetization direction. The nMOS transistor is provided between the write bit line and the magnetization fixed layer.
    Type: Application
    Filed: August 10, 2012
    Publication date: February 14, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazumasa SUZUKI
  • Publication number: 20130040434
    Abstract: In a semiconductor device having element isolation made of a trench-type isolating oxide film 13, large and small dummy patterns 11 of two types, being an active region of a dummy, are located in an isolating region 10, the large dummy patterns 11b are arranged at a position apart from actual patterns 9, and the small dummy patterns 11a are regularly arranged in a gap at around a periphery of the actual patterns 9, whereby uniformity of an abrading rate is improved at a time of abrading an isolating oxide film 13a is improved, and surface flatness of the semiconductor device becomes preferable.
    Type: Application
    Filed: October 5, 2012
    Publication date: February 14, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: RENESAS ELECTRONICS CORPORATION
  • Publication number: 20130038360
    Abstract: Provided is a timing control device including: a storage unit that stores multiple pieces of timing control information including identification information and expected value data; a first selector that selectively outputs any of the multiple pieces of timing control information; a second selector that selectively outputs any of data items output from data output devices based on the identification information; a reference data generation unit that generates reference data based on expected value data and a data item output from the second selector in synchronization with a switching of the timing control information; a comparator that compares the reference data with the data item output from the second selector and outputs a coincidence signal when the reference data and the data item coincide with each other; and an output control unit that outputs a timing signal according to the coincidence signal.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 14, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Atsushi TAKAHASHI