Abstract: A power supply selection/detection circuit to select one main power supply from a plurality of external power supplies includes a resistance element with one end connected to an external power supply and another end connected to the main power supply, a first voltage detector to receive a voltage of the external power supply and detect a voltage of the external power supply, a second voltage detector to detect a voltage between the ends of the resistance element, and a switch connected between the external power supply and a ground to short-circuit or open-circuit between the external power supply and the ground according to an output of the second voltage detector. The resistance element and the first voltage detector are disposed for each of the plurality of external power supplies, and the second voltage detector and the switch are disposed for at least one of the plurality of external power supplies.

Abstract: A semiconductor device using resistive random access memory (ReRAM) elements and having improved tamper resistance is provided. The semiconductor device is provided with a unit cell which stores one bit of cell data and a control circuit. The unit cell includes n ReRAM elements (n being an integer of 2 or larger). At least one of the ReRAM elements is an effective element where the cell data is recorded. In reading the cell data, the control circuit at least selects the effective element and reads data recorded thereon as the cell data.

Abstract: A method and apparatus are provided for reliably paging a mobile terminal in the idle mode, even in an instance in which the mobile terminal is subjected to interference from a CSG cell. In this regard, a method is provided that includes causing an indication of an inter-cell interference coordination (ICIC) paging period to be provided to the mobile terminal. The indication of the ICIC paging period includes an ICIC paging period TICIC and a number NABS of consecutive almost blank subframes (ABS) subframes in which a paging message is to be expected. The method also determines, for a respective ICIC paging period, the NABS nearest ABS subframes of the CSG cell relative to a paging occasion (PO) subframe of the mobile terminal. A paging message is also provided to the mobile terminal in one of the NABS nearest ABS subframes of the CSG cell.

Abstract: A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.

Abstract: A high frequency circuit and a high frequency module are provided, in which the accuracy of compensation operation is improved in compensating by digital control. The amplification gain of an amplification element of an amplifier unit is controlled by a bias current of a bias control unit. A process monitoring circuit of a calibration circuit includes a first and a second element characteristic detector and a voltage comparator. The detectors convert the current of replica elements into a first and a second detection voltage. The voltage comparator compares a first and a second detection voltage and supplies a comparison output signal to a search control unit. Responding to the comparison output signal of the comparator and a clock signal of a clock generating unit, the controller generates a multi-bit digital compensation value according to a predetermined search algorithm, and the bias control unit of the second detector is feedback-controlled.

Abstract: A semiconductor device includes a memory cell. The memory cell includes: a magnetic recording layer formed of ferromagnetic material; first and second magnetization fixed layers coupled to the magnetic recording layer; first and second reference layers opposed to the magnetic recording layer; and first and second tunnel barrier films inserted between the magnetic recording layer and the first and second reference layers, respectively. The first magnetization fixed layer has a magnetization fixed in a first direction, and the second magnetization fixed layer has a magnetization fixed in a second direction opposite to the first direction. The first and second reference layers and the first and second tunnel barrier films are positioned between the first and second magnetization fixed layers.

Abstract: A method of cutting an electrical fuse including a first conductor and a second conductor, the first conductor including a first cutting target region, the second conductor branched from the first conductor and connected to the first conductor and including a second cutting target region, which are formed on a semiconductor substrate, the method includes flowing a current in the first conductor, causing material of the first conductor to flow outward near a coupling portion connecting the first conductor to the second conductor, and cutting the first cutting target region and the second cutting target region.

Abstract: In a high-frequency circuit, it is necessary to block galvanically between active elements such as transistors and between an active element and an external terminal, and thus MIM capacitors or the like are used frequently. Among these MIM capacitors, one coupled to the external terminal is easily affected by static electricity from outside, which easily causes a problem of electro-static breakdown or the like. The present invention is a semiconductor integrated circuit device formed over a semi-insulating compound semiconductor substrate in which a first electrode of an MIM capacitor electrically coupled to an external pad is electrically coupled to the semi-insulating compound semiconductor substrate, and on the other side, a second electrode of the MIM capacitor is electrically coupled to the semi-insulating compound semiconductor substrate.

Abstract: A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103; a flip-chip pad 111, provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111. Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105, a capacitive film 109 and a capacitor element 110.

Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

Abstract: In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have.

Abstract: In an n-channel HK/MG transistor including: a gate insulating film made of a first high dielectric film containing La and Hf; and a gate electrode which is formed of a stacked film of a metal film and a polycrystalline Si film and which is formed in an active region in a main surface of a semiconductor substrate and surrounded by an element separation portion formed of an insulating film containing oxygen atoms, a second high dielectric film which contains Hf but whose La content is smaller than a La content of the first high dielectric film is formed below the gate electrode which rides on the element separation portion, instead of the first high dielectric film.

Abstract: A semiconductor device includes a memory cell. The memory cell includes: a magnetic recording layer formed of ferromagnetic material; first and second magnetization fixed layers coupled to the magnetic recording layer; a plurality of reference layers opposed to the magnetic recording layer; and a plurality of tunnel barrier films respectively inserted between the magnetic recording layer and the reference layers. The first magnetization fixed layer has a magnetization fixed in a first direction, and the second magnetization fixed layer has a magnetization fixed in a second direction opposite to first direction. The reference layers each have a magnetization fixed in the first direction or the second direction. The reference layers and the tunnel barrier layers are positioned between the first and second magnetization fixed layers.

Abstract: The present invention discloses an apparatus, a method and a computer program for mapping and allocating available television white space channels for a terminal requesting resources. The mapping is based on the data of available overlapping TV white space channels within a geographical tracking area and coexistence with other cellular secondary systems within the area. Furthermore, a location for a moving mode II device may be tracked periodically. The geo-location accuracy of the mode II device affects the TV white space resources which can be allocated to the device.

Abstract: The invention teaches a solution, for example, for Long Term Evolution (LTE) networks. The solution comprises determining a measurement pattern for at least one automatic gain control tracking loop when resource restrictions have been configured for a user equipment, the resource restrictions comprising at least one measurement restriction pattern, wherein each automatic gain control tracking loop is associated with at least one measurement restriction pattern; and performing automatic gain control measurements according to the measurement patterns of the at least one automatic gain control tracking loop.

Abstract: A method and apparatus are provided for facilitating the creation of an intra-system interface between systems operating in an unlicensed spectrum, such as between respective access points of first and second LTE systems that use the same radio resources within an unlicensed spectrum, such as within the TV white spaces. In the context of a method, configuration messages may be caused to be sent to first and second systems regarding creation of an intra-system interface. The method may also receive configuration message responses including address information for first and second access points of the first and second systems, respectively. The method may additionally cause a message to be sent to the first system to trigger the first system to initiate establishment of the intra-system interface with the second system.

Abstract: The present invention provides ABS precision improving means under ADPLL environment or environment close to the ADPLL environment and realizes shortening of process time of the ABS. In a digital frequency comparator in an ABS circuit, a DFF for storing an initial phase difference in a DPE signal output from a DPFD is prepared. Immediately after start of ABS operation, a DPE signal output from the DPFD is recorded as a signal expressing an initial phase difference in an internal circuit of the DPFD into the DFF. After that, the digital frequency comparator performs ABS by using a signal obtained by subtracting the initial phase error recorded in the DFF from an input DPE signal, thereby realizing high-speed and stabilized ABS operation.

Abstract: When a semiconductor element is formed over a wiring substrate, the number of manufacturing steps of the wiring substrate is reduced. A first wiring 232 is disposed over one surface of a core layer 200. A semiconductor layer 236 is formed over the first wiring 232 and over one surface of the core layer 200 located around the first wiring 232. The first wiring 232 and the semiconductor layer 236 form a semiconductor element. In the present embodiment, the semiconductor element is a transistor 230, in which the first wiring 232 is the gate electrode, and has a gate insulating film 234 between the semiconductor layer 236 and the first wiring 232.

Abstract: A driving method of a liquid crystal display panel having a source line and a counter electrode, includes driving the counter electrode to a first potential, driving the, counter electrode to a second potential being different from the first potential, setting the counter electrode and the source line to a third potential by short-circuiting the counter electrode and the source line to an interconnection having a potential between the first potential and the second potential, and driving the source line to a potential corresponding to an image data. The setting of the counter electrode and the source line to the third potential occurs in a period of one frame.

Abstract: A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.