Abstract: A frequency-voltage converting circuit 13 is composed of a switch unit including switches SW1 and SW2, electrostatic capacitive elements C and C10 to C13, and switches CSW0 to CSW3. The electrostatic capacitive elements C10 to C13 are composed of elements having mutually different absolute values of capacitance and are provided so as to cover a frequency range intended by a designer. The electrostatic capacitance values are weighted by, for example, 2. The electrostatic capacitive elements C11 to C13 are selected by, for example, the switches CSW0 to CSW3 based on 4-bit frequency adjustment control signals SELC0 to SELC3, thereby carrying out frequency switching.

Abstract: For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

Abstract: There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.

Abstract: In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.

Abstract: A semiconductor device includes a transistor with a substrate on which source and drain regions, both of a first conductivity type, and a channel region of a second conductivity type between the source and drain are formed, and a gate electrode formed in the channel region to bury a trench formed so the depth thereof changes intermittently in the width direction of the gate. In the channel region, each on a surface of the substrate and in a bottom portion of the trench, there are formed a second high-concentration region and a first high-concentration region, and the dopant concentration of the second conductivity type is higher than the dopant concentration of the second conductivity type in portions sideward from the trench. The dopant concentration of the second conductivity type in the first high-concentration region is higher than the dopant concentration of the second conductivity type in the second high-concentration region.

Abstract: A semiconductor device which uses a semiconductor substrate having a TEG pattern to reduce defects induced by dicing. The semiconductor device includes a semiconductor substrate which is to be or has been divided into individual semiconductor chips by dicing; an interlayer insulating layer formed over the semiconductor substrate; a seal ring provided in the interlayer insulating layer and formed along the periphery of the semiconductor chip; and a TEG wiring having one end coupled to the seal ring and the other end extending toward an end face of the periphery of the semiconductor chip.

Abstract: A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.

Abstract: In an IGBT, defects generated by ion implantation for introduction of the P-type collector region or N-type buffer region into the N?-type drift region near the N-type buffer region remain to improve the switching speed, however the leak current increases by bringing a depletion layer into contact with the crystal defects at the off time. To avoid this, an IGBT is provided which includes an N-type buffer region having a higher concentration than that of an N?-type drift region and being in contact with a P-type on its backside, and a defect remaining region provided near the boundary between the N-type buffer region and the N?-type drift region. The N?-type drift region located on the front surface side with respect to the defect remaining region is provided with an N-type field stopping region having a higher concentration than that of the N?-type drift region.

Abstract: The generation of a variation in properties of vertical transistors is restrained. A vertical MOS transistor is formed in a semiconductor substrate. A first interlayer dielectric film and a first source wiring are formed over the front surface of the substrate. The first source wiring is formed over the first interlayer dielectric film, and is overlapped with the vertical MOS transistor as viewed in plan. Contacts are buried in the first interlayer dielectric film. Through the contacts, an n-type source layer of vertical MOS transistor is coupled with the first source wiring. Openings are made in the first source wiring.

Abstract: An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.

Abstract: A data line driving circuit for a display panel includes a plurality of output circuits, a bias circuit, and a plurality of switches. Each of the plurality of output circuits includes an electric current source which supplies electric current in response to a bias signal, and supplies a data voltage by using the electric current to a corresponding one of a plurality of data lines arranged in the display panel. The bias circuit generates the bias signal, and supplies the bias signal to the plurality of output circuits through bias wirings. The plurality of switches is provided between the bias circuit and the plurality of output circuits, and cuts off the bias wirings in response to a control signal.

Abstract: A data processing system is provided, which can realize speeding up and facilitation of data processing using a program and a parameter of a scale larger than the maximum storage capacity of an available on-chip nonvolatile memory. A program and a parameter of a scale larger than the maximum storage capacity of the on-chip nonvolatile memory are stored in a nonvolatile semiconductor memory device coupled to the exterior of a semiconductor data processing device, and responding to the determination result of the information supplied from the exterior, the semiconductor data processing device downloads an internally required program and parameter from the nonvolatile semiconductor memory device, and rewrites the on-chip nonvolatile memory. When the program is rewritten, software reset processing is performed to execute the program from a starting address.

Abstract: An authentication method is provided which is capable of performing message authentication within an allowable time regardless of the magnitude of the number of messages and performing message authentication high in accuracy within a range for which the allowable time allows. Upon transmission by wireless communications with another mobile or a fixed station, a message authentication code of communication data and a digital signature are generated (S200 and S300). The generated message authentication cod and digital signature are transmitted with being added to the communication data. Upon reception, whether authentication should be done using either one of the message authentication code and the digital signature included in received information is determined according to its own state for the authentication (S400 and S500). This state includes, for example, a load state of a central processing unit or the like that performs an authentication process.

Abstract: To provide a multiprocessor capable of easily sharing data and buffering data to be transferred. Each of a plurality of shared local memories is connected to two processors of a plurality of processor units, and the processor units and the shared local memories are connected in a ring. Consequently, it becomes possible to easily share data and buffer data to be transferred.

Abstract: In the manufacturing steps of a power-type semiconductor device, after grinding the back surface of the semiconductor wafer, when a metal film is deposited by sputtering deposition over the back surface of the wafer in a preheated state, the wafer is contained in an annular susceptor, and processed. A radial vertical cross section of the annular shape of the susceptor has a first upper surface closer to a horizontal surface for holding a peripheral portion of the top surface of the semiconductor wafer against gravity, and a second upper surface continued to and located outside the first upper surface and closer to a vertical surface for holding a side surface of the semiconductor wafer against lateral displacement.

Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Abstract: A semiconductor device includes an electrode pad provided on a semiconductor chip, the electrode pad includes aluminum (Al) of between 50% wt. and 99.9% wt. and further includes copper (Cu), a coupling ball that primarily includes Cu, the coupling ball being coupled to the electrode pad so that a CuAl2 layer, a CuAl layer, a layer including one of Cu9Al4 and Cu3Al2, and the coupling ball are vertically stacked in this order on the electrode pad, and an encapsulating resin that includes a halogen of less than or equal to 1000 ppm, the encapsulating resin covering at least the electrode pad and a junction between the electrode pad and the coupling ball.

Abstract: A data driver for display panels includes: multiple driver output terminals coupled to multiple data lines of a display panel; and multiple output circuits that output output signals from the driver output terminals. Each output circuit includes: an output buffer that outputs an output signal; a first resistor having one end coupled to one of the driver output terminals; a first switch and a second resistor coupled in series between an output node of the output buffer and the other end of the first resistor; and a second switch coupled in parallel to the first switch and the second resistor between the output node of the output buffer and the other end of the first resistor.

Abstract: A circuit includes a first node, a second node, a third node between the first and second nodes, a first field effect transistor coupled between the first and third nodes, a second field effect transistor coupled to the third node including a second gate terminal coupled to a second resistor, a third field effect transistor coupled to the third node including a third gate terminal coupled to a third resistor, a first capacitor coupled to the second field effect transistor, a second capacitor coupled to the third field effect transistor, a third capacitor coupled between the second and third nodes, and a fourth field effect transistor coupled between the second and third nodes.

Abstract: In a semiconductor device having an LDMOSFET, a source electrode is at the back surface thereof. Therefore, to reduce electric resistance between a source contact region in the top surface and the source electrode at the back surface, a poly-silicon buried plug is provided which extends from the upper surface into a P+-type substrate through a P-type epitaxial layer, and is heavily doped with boron. Dislocation occurs in a mono-crystalline silicon region around the poly-silicon buried plug to induce a leakage failure. The semiconductor device has a silicon-based plug extending through the boundary surface between first and second semiconductor layers having different impurity concentrations. At least the inside of the plug is a poly-crystalline region. Of the surface of the poly-crystalline region, the portions located on both sides of the foregoing boundary surface in adjacent relation thereto are each covered with a solid-phase epitaxial region.