Abstract: There is provided a sensor network information collection mechanism in which, after a UE has decided to become part of an information collecting operation for collecting information from a local sensor network, a signaling transmitted from a managing node of a local sensor network is received and processed. A communication network control element is informed about the willingness to become an information collector by sending a report message comprising measurement results derived from the signaling received from the managing node of the local sensor network. When receiving a gateway allocation message indicating that the UE is determined to be a gateway element to the local sensor network, the information collecting operation is started wherein sensor nodes of the local sensor network are woke up, and a traffic flow direction in the local sensor network is set in accordance with the managing node identity to which the UE is accessed.

Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.

Abstract: A semiconductor device includes an interposer having a base member including a first surface and a second surface opposite to the first surface, a first interconnect formed on the first surface of the base member, a first insulating film formed on the first surface of the base member, a first external terminal and a second external terminal neighboring the first external terminal formed on the second surface of the base member, a second interconnect formed on the second surface of the base member and passing between the first external terminal and the second external terminal, and a second insulating film formed on the second surface of the base member, a semiconductor chip mounted on the first insulating film, a sealing resin formed on the first insulating film and sealing the semiconductor chip. The second insulating film has an opening so that the second interconnect is exposed in an area.

Abstract: Provided is a technology of suppressing, in forming an initial ball by using an easily oxidizable conductive wire and pressing the initial ball onto a pad to form a press-bonded ball, an initial ball from having a shape defect, thereby reducing damage to the pad. To achieve this, a ball formation unit is equipped with a gas outlet portion for discharging an antioxidant gas and a discharging path through this gas outlet portion is placed in a direction different from a direction of introducing the antioxidant gas into a ball formation portion. Such a structure widens a region for discharging the antioxidant gas, making it possible to prevent a gas flow supplied from the side of one side surface of the ball formation portion from being reflected by the other side surface facing with the one side surface and thereby forming a turbulent flow.

Abstract: A first cladding layer is formed above a substrate. An active layer is formed above the first cladding layer. An optical confinement layer is formed above the active layer. A pair of band-like current block layers is formed above the optical confinement layer and opposed to each other through an opening extending in a first direction. A second cladding layer is formed on the current block layers and the optical confinement layer. A contact layer is formed above the second cladding layer. A mesa portion is formed by being sandwiched between a pair of groove portions. The current block layers and the opening are included in the mesa portion, and an end of each current block layer on an opposite side to the opening and a side wall of the mesa portion are spaced apart by a predetermined value or more in a second direction.

Abstract: A data line driving circuit for a liquid crystal display device comprising: a plurality of first data lines applied with a positive potential, a plurality of second data lines applied with a negative potential, comparison units that compare with a reference voltage at least one of a potential at a first common line connected to the plurality of first data lines and a potential at a second common line connected to the plurality of second data lines, and switches that are controlled so that the first data lines and the second data lines are set to a connection state or an interruption state according to a comparison result by the comparison units.

Abstract: Apparatus and method for communication are provided. The solution comprises communicating on a synchronised shared channel having a frame structure comprising symbols; receiving from a network element a given number for each frame or sub frame, and during the given number of symbol periods in the beginning of a frame or sub frame measuring interference and making a decision whether to transmit or not during the rest of the symbol periods of the frame or sub frame.

Abstract: Provided is a technology capable of inhibiting a shield film formed over a surface of a sealing body from peeling from the surface of the sealing body, and inhibiting a part of the shield film from bulging from the surface of the sealing body. The present invention is characterized in that a peeling-prevention-mark formation region is provided so as to surround a product-identification-mark formation region, and a plurality of peeling prevention marks are formed in the peeling-prevention-mark formation region. That is, the present invention is characterized in that the region of the surface region of the sealing body which is different from the product-identification-mark formation region is defined as the peeling-prevention-mark formation region, and the peeling prevention marks are formed in the peeling-prevention-mark formation region.

Abstract: In a sense circuit for DRAM memory cell a switch is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.

Abstract: To increase the manufacturing yield of semiconductor devices by improving a joint failure of a bump electrode. In a semiconductor device in which a plurality of boding pads 4 formed on a front surface of a semiconductor chip 3 and a plurality of leads 2 are connected via a plurality of bump electrodes 5, respectively, the upper surface of the leads 2 is formed into a semi-glossy surface having a roughness a maximum height (Ry) of which is in a range greater than 0 ?m and not greater than 20 ?m (0 ?m<maximum height (Ry)?20 ?m), not into a planar surface (maximum height (Ry)=0).

Abstract: The invention of the present application provides an IE-type trench IGBT. In the IE-type trench IGBT, each of linear unit cell areas that configure a cell area is comprised principally of linear active and inactive cell areas. The linear active cell area is divided into an active section having an emitter region and an inactive section as seen in its longitudinal direction.

Abstract: Provided is a semiconductor device having a wiring layer formed of damascene wiring. The semiconductor device includes: a first wiring having a width equal to or larger than 0.5 ?m; a second wiring adjacent to the first wiring and arranged with a space less than 0.5 ?m from the first wiring; and a third wiring adjacent to the second wiring and arranged with a space equal to or smaller than 0.5 ?m from the first wiring. In the semiconductor device, the second wiring and the third wiring are structured to have the same electric potential.

Abstract: An electronic device capable of balancing both light transmitting and receiving performance and mounting reliability is provided. The electronic device includes an element (light receiving element), a transparent layer, and a sealing resin layer. The element is, for example, a semiconductor element and has an optically functional region having an optical function (for example, light receiving or light emission) on one face. The transparent layer is located on the optically functional region, directly comes in contact with the one face of the light receiving element, and is optically transparent. The sealing resin layer seals sides of the transparent layer and one face of the light receiving element, does not coat an upper face of the transparent layer, and is mixed with filler that improves rigidity.

Abstract: A horizontal synchronization detection device includes a pulse detection portion that detects a pulse in a horizontal synchronization signal contained in a video signal and acquires a pulse width of the detected pulse, a synchronization pulse decision portion that determines the pulse satisfying a condition that a difference between its pulse width and a reference pulse width is within a first predetermined range as a synchronization pulse, a mean pulse width acquisition portion that averages out a pulse width of the synchronization pulse for each field and obtains a mean pulse width thereof, and a reference pulse width correction portion that determines, for each synchronization pulse in a current field, whether a difference between its pulse width and the mean pulse width in a previous field is within a second predetermined range, and corrects the reference pulse width and/or the first predetermined range based on the determination result.

Abstract: One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor.

Abstract: A P-channel MOS transistor MP1 is provided between an input voltage Vin and the low-voltage circuit. The cathode of a first zener diode Z1 is connected to a node between the input voltage Vin and the source of the P-channel MOS transistor MP1. The anode of the first zener diode Z1 is branched into two lines at a branch node N1, and one of the two lines is connected to a ground through a resistor R1. The other of the two lines is connected to the gate of the P-channel MOS transistor MP1. The cathode of a second zener diode Z2 is connected to a node between the low-voltage circuit and the drain of the P-channel MOS transistor MP1. The anode of the second zener diode Z2 is connected to a ground.

Abstract: A DMA transfer control device comprises: a DMA arbiter performing DMA transfer for each DMA channel formed by a combination of a memory and a plurality of input/output devices and DMA controller circuits controlling the DMA arbiter; a judgment unit and a transfer time calculation unit calculating a next DMA transfer scheduled time based on the DMA transfer size for a DMA transfer request and a judgment time. A timer counter timing the judgment time at a unit time interval, and a comparator comparing the judgment time where a DMA transfer request arrives with the DMA transfer scheduled time are also provided, and the judgment unit sends the DMA transfer permission to the DMA arbiter upon an output of the comparator indicating the judgment time is not earlier than the DMA transfer scheduled time. Data is efficiently transferred by dynamically controlling DMA transfer.

Abstract: A semiconductor device has an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. The conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. After etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate, a channel region and a source region are formed by ion implantation so that the semiconductor device is free from occurrence of a source offset.

Abstract: Disclosed is a semiconductor device which includes a semiconductor chip and a base substrate. The semiconductor chip includes a semiconductor substrate, an interconnect layer and a high-frequency interconnect. The interconnect layer is provided on the substrate. The high-frequency interconnect is formed within the interconnect layer. The semiconductor chip is mounted onto the base substrate. An electromagnetic shield layer is provided between the high-frequency interconnect and the interconnect.

Abstract: A controlling unit disposed in a PLL circuit controls a phase interpolator to gradually change a phase shift amount applied to a phase shift signal C_PS by a unit of basic delay amount ? at a timing predetermined in accordance with a modulation profile of an SSC. Further, the controlling unit controls a total phase shift amount applied to the phase shift signal C_PS output from the phase interpolator in one period of a feedback clock signal C_FB obtained by dividing frequency of the phase shift signal C_PS in a way that a difference between the total phase shift amount and a total phase shift amount in a previous one period of C_FB is always equal to or less than the basic delay amount ?.