Abstract: A display panel drive apparatus includes a source driver that drives each unit dot in accordance with a time-divisional clock, and a booster circuit that generates a supply voltage to be supplied to the source driver based on a clock having a rising edge and a falling edge each coinciding with an off-period of the time-divisional clock. The display panel drive apparatus performs a time-divisional driving operation during one horizontal period.

Abstract: A semiconductor device having a digital region and an analog region embedded therein has an annular seal ring which surrounds the outer circumference of the digital region and the analog region in a plan view; a guard ring which is provided in the area surrounded by the seal ring, between the digital region and the analog region, so as to isolate the analog region from the digital region, and so as to be electrically connected to the seal ring; and an electrode pad which is electrically connected to the guard ring in the vicinity of the guard ring.

Abstract: A microcomputer includes a CPU, a protection information storage configured to store memory protection information specifying an access permission or prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information and a reset apparatus configured to invalidate the memory protection information stored in the protection information storage according to a reset request signal output from the CPU.

Abstract: The electronic device, which allows inhibiting the breaking-away of the element from the frame member, even if the temperature change of the electronic device is repeated, and the process for manufacturing the electronic device, are achieved. An electronic device includes a photo-sensitive element formed in a wafer, a frame member installed on the wafer to surround a functional unit, and an encapsulating resin layer filling a circumference of the frame member.

Abstract: A power supply control apparatus includes an output transistor coupled between a first power supply line and an output terminal, the output terminal being configured to be coupled with a load, a discharge transistor coupled between a gate of the output transistor and the output terminal, and rendered conductive when the output transistor is brought into a non-conduction state, a negative voltage control unit coupled between the first power supply line and the gate of the output transistor, and bringing the output transistor into a conduction state when the counter electromotive voltage applied to the output terminal from the load exceeds a predetermined value, a diode having a cathode coupled with the first power supply line, and an anode, a third resistor provided between the anode of the diode and a second power supply line, and a compensation transistor coupled between the second power supply line and the output terminal.

Abstract: A field-effect transistor (142) includes a lowly p-doped region 110 formed on a surface of a substrate (102), an n-doped drain region 112 and n-doped source region 114 arranged on a surface of the lowly p-doped region 110, and a device isolation insulating film 132 and device isolation insulating film 134. Here, the device isolation insulating film 132 is formed greater in film thickness than the device isolation insulating film 134; and in the n-doped source region 114, the peak concentration section having a highest dopant concentration is formed in a deeper position than in the n-doped drain region 112.

Abstract: A semiconductor device includes a first oscillator that generates a first clock signal, a second oscillator that generates a second clock signal in response to the first clock signal, a third oscillator that generates a third clock signal, a counter that counts a signal corresponding to the first clock signal or a signal corresponding to the second clock signal during a predetermined period that is set based on the third clock signal to generate an overflow signal indicating that a count value of the signal corresponding to the first clock signal or the signal corresponding to the second clock signal exceeds a predetermined value, and an abnormality notice unit that receives the overflow signal to generate an abnormal signal indicating that an abnormal oscillation occurs in at least one of the first to third clock signals.

Abstract: A receiving circuit in accordance with an exemplary aspect of the present invention includes a first voltage-dividing circuit that outputs a first input signal obtained by voltage division of one of differential signals based on the resistance ratio between first and second resistors, a second voltage-dividing circuit that outputs a second input signal obtained by voltage division of the other of the differential signals based on the resistance ratio between third and fourth resistors, a differential amplifier that amplifies the differential component between the first and second input signals, a common-mode voltage detection circuit that detects the common-mode voltage of the differential signals, and a bias voltage switching circuit that switches the voltage value of a bias voltage based on the common-mode voltage.

Abstract: A video signal processing apparatus (and method) includes a section determination unit which detects a non-equidistant section having different intervals between a plurality of sample points set for a range from a minimum signal level to a maximum signal level of a video signal to be inputted, a correction level holding unit which holds a signal level of a video signal after correction for each sample point as a correction level, and an interpolation computation unit which obtains a signal level of the video signal after correction corresponding to the signal level of the inputted video signal by executing cubic interpolation computation with reference to the correction level held by the correction level holding unit

Abstract: A data processing apparatus (and method of data processing) that creates a plurality of audio packs from audio streams including a plurality of audio frames, includes an audio buffer occupancy calculator that calculates an occupancy of an audio buffer for temporarily storing the audio streams, and a payload length setting section that defines a predetermined overflow limit capacity for the audio buffer, and that determines a payload length of each of the audio packs based on a difference between the overflow limit capacity and the occupancy.

Abstract: A computer device which performs logic synthesis using hardware description and a component in a cell library and generates a net list of a logic circuit including a series path of a clock synchronous sequential circuit and a combinational circuit performs optimization processing for decreasing the number of gate stages in a critical path between sequential circuits in the data path by using a third sequential circuit having a negative-logic input terminal and a negative-logic non-inverted output terminal and a fourth sequential circuit having a negative-logic input terminal and a negative-logic inverted output terminal in addition to a first sequential circuit having a positive-logic input terminal and a positive-logic non-inverted output terminal and a second sequential circuit having a positive-logic input terminal and a positive-logic inverted output terminal.

Abstract: An improved method of forming a semiconductor device including an interconnect layer formed using multilayer hard mask comprising metal mask and dielectric mask is provided. To form the second opening pattern being aligned to the first pattern, after the multilayer hard mask is used at the first step, then the dielectric mask is used to form a damascene structure in an insulator layer at the second step followed by removing the metal mask.

Abstract: The electrical characteristics of a semiconductor device are enhanced. In the package of the semiconductor device, there are encapsulated first and second semiconductor chips with a power MOS-FET formed therein and a third semiconductor chip with a control circuit for controlling their operation formed therein. The bonding pads for source electrode of the first semiconductor chip on the high side are electrically connected to a die pad through a metal plate. The bonding pad for source electrode of the second semiconductor chip on the low side is electrically connected to lead wiring through a metal plate. The metal plate includes a first portion in contact with the bonding pad of the second semiconductor chip, a second portion extended from a short side of the first portion to the lead wiring, and a third portion extended from a long side of the first portion to the lead wiring.

Abstract: Disclosed is a semiconductor integrated circuit device that includes a ring oscillator circuit, performs a proper oscillation operation, and expands the range of oscillation frequency variation. The ring oscillator circuit includes, for instance, plural differential amplifier circuits. MOS transistors are respectively added to input nodes of a differential pair of the differential amplifier circuits. Further, gate control circuits are incorporated to control the gates of the MOS transistors, respectively. The gate control circuits cause the MOS transistors to function as an amplitude limiter circuit in mode 3, exercise control to turn off the amplitude limiter circuit in mode 2, and use the amplitude limiter circuit to start oscillation in mode 1.

Abstract: Miniaturization and acceleration of the operating speed of a System In Package (SIP) type semiconductor device in which a memory chip and a microcomputer chip are mounted over a wiring board are promoted. When mounting a microcomputer chip and a memory chip over an upper surface of a wiring board, the memory chip is disposed such that second conductive pads of the wiring board arranged along a first chip side (a side along which data system electrode pads are arranged) of the memory chip are positioned, in the plan view, in a region between an extended line of a third chip side of the microcomputer chip and an extended line of a fourth chip side of the microcomputer chip. Thus, a length of a data system wiring for coupling a data system electrode pad of the microcomputer chip with the data system electrode pad of the memory chip is minimized.

Abstract: A method includes: forming an device isolation region in a substrate to divide the device isolation region into a first and a second diffusion regions; forming a target film on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.

Abstract: A method includes: forming an device isolation region in a substrate to divide the device isolation region into first and second diffusion regions; forming a target film on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer by using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer for isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.

Abstract: A method for cutting an electric fuse formed on a semiconductor substrate by applying a predetermined electric voltage between a first interconnect and a second interconnect to flow an electric current in the electric fuse such that the electric conductor is flowed toward outside from the second interconnect to form a void region between the via and the first interconnects or in the via.

Abstract: A generation of a void in a recessed section is inhibited. A method for manufacturing a semiconductor device includes: an operation of forming recessed sections in an insulating film, which is formed on a semiconductor substrate; an operation of forming a seed film in the recessed section; an operation of forming a cover metal film in the recessed section; an operation of selectively removing the cover metal film to expose the seed film over the bottom section of the recessed section; and an operation to carrying out a growth of a plated film to fill the recessed section by utilizing the seed film exposed in the bottom section of the recessed section as a seed.

Abstract: Improvement in the accuracy of a temperature sensor is aimed at, suppressing the number of the test temperature in a test process. The semiconductor device comprises a coefficient calculation unit which calculates up to the N-th order coefficient (N is an integer equal to or greater than one) of a correction function as an N-th order approximation of a characteristic function indicating correspondence relation of temperature data measured by a temperature sensor unit and temperature, based on N+1 pieces of the temperature data including a theoretical value at a predetermined temperature in the characteristic function and N measured values of the temperature data measured by the temperature sensor unit at N points of temperature; and a correction operation unit which generates data including information on temperature, by performing calculation using the correction function to which the coefficients calculated are applied, based on temperature data measured by the temperature sensor unit.