Patents Assigned to RENESAS
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Publication number: 20120200441Abstract: An output circuit includes a connection switch and an operation unit. The connection switch receives first and second voltages from first and second terminals, respectively, selects and outputs the first voltage or the second voltage for first to third intermediate terminals, including selection of the same voltage and switches assignment of the first and second voltages to the first to third intermediate terminals responsive to a connection switching signal. The operation unit receives the voltages assigned to the first to third intermediate terminals and outputs to an output terminal a voltage obtained by performing a predetermined operation on the voltages.Type: ApplicationFiled: April 16, 2012Publication date: August 9, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Junichiro ISHII, Hiroshi TSUCHI
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Publication number: 20120199904Abstract: A field drain insulating part has a first insulating film and a high dielectric constant insulating film. The first insulating film is positioned at least in the center of the field drain insulating part in a plan view. The high dielectric constant insulating film is positioned at a part close to a drain region in the edge of the bottom surface of the field drain insulating part, and has a higher dielectric constant than the first insulating film. The high dielectric constant insulating film is not positioned in the center of the field drain insulating part in a plan view.Type: ApplicationFiled: January 26, 2012Publication date: August 9, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Kenji SASAKI
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Publication number: 20120200335Abstract: One high-frequency switch Qm supplied with transmit and receive signals to ON, and another high-frequency switch Qn supplied with a signal of another system to OFF are controlled. In the other high-frequency switch Qn, to set V-I characteristics of near-I/O gate resistances Rg1n-Rg3n of a near-I/O FET Qn1 near to a common input/output terminal I/O connected with an antenna are set to be higher in linearity than V-I characteristics of middle-portion gate resistances Rg3n and Rg4n of middle-portion FETs Qn3 and Qn4. Thus, even in case that an uneven RF leak signal is supplied to near-I/O gate resistances Rg1n-Rg3n, and middle-portion gate resistances Rg3n and Rg4n, the distortion of current flowing through the near-I/O gate resistances Rg1n-Rg3n near to the input/output terminal I/O can be reduced.Type: ApplicationFiled: April 16, 2012Publication date: August 9, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Shigeki Koya, Shinichiro Takatani, Takashi Ogawa, Akishige Nakajima, Yasushi Shigeno
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Publication number: 20120201156Abstract: In a wireless communication device for performing plural wireless communications with different standards using the same frequency band, degradation of communication quality and communication speed due to communication interference is prevented, while drop in throughput and occurrence of frame loss are prevented. A first wireless communication section first performs wireless communication using a first frequency band and a second wireless communication section performs second wireless communication using a second frequency band with which at least a part of the first frequency band overlaps.Type: ApplicationFiled: February 1, 2012Publication date: August 9, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroki SUGIMOTO, Koji KUBOTA
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Publication number: 20120202342Abstract: A method of manufacturing a semiconductor device includes depositing a wiring metal layer on a photoresist layer and a portion of a first layer of a gate lead-out electrode which is exposed via an opening, lifting-off a wiring metal layer formed on the photoresist layer forming an interlayer insulation film over the entire surface including the first layer and the wiring metal layer, selectively removing the interlayer insulation film thereby forming a contact via reaching a source region formed in a cell region, and forming a source electrode on the interlayer insulation film and electrically connecting a source electrode with the source region.Type: ApplicationFiled: April 18, 2012Publication date: August 9, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Kouji NAKAJIMA
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Publication number: 20120203941Abstract: A serial communication device has: a MAC (Media Access Control), a mask circuit and a buffer. The MAC conforms to Serial Media Independent Interface specification and outputs an identical segment data for plural times within a unit period. The mask circuit is configured to mask a predetermined segment data out of the plurality of identical segment data and to output the other segment data out of the plurality of identical segment data. The buffer is configured to receive the segment data output from the mask circuit and to output the received segment data to a physical layer device in synchronization with a clock signal.Type: ApplicationFiled: April 19, 2012Publication date: August 9, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Tomofumi IIMA
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Publication number: 20120199470Abstract: A method for manufacturing an MTJ film includes forming a first ferromagnetic layer; forming a tunnel barrier layer over the first ferromagnetic layer; and forming a second ferromagnetic layer over the tunnel barrier layer. The first ferromagnetic layer is a Co/Ni stacked film having perpendicular magnetic anisotropy. The step for forming a tunnel barrier layer includes repeating unit film formation treatment n times (n is an integer of 2 or more). The unit film formation treatment includes the steps of: depositing an Mg film by a sputtering method; and oxidizing the deposited Mg film. A film thickness of the deposited Mg film in the first unit film formation treatment is 0.3 nm or more and 0.5 nm or less. A film thickness of the deposited Mg film in the second unit film formation treatment or later is 0.1 nm or more and 0.45 nm or less.Type: ApplicationFiled: February 2, 2012Publication date: August 9, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kaoru MORI, Eiji KARIYADA, Katsumi SUEMITSU, Norikazu OHSHIMA
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Publication number: 20120200440Abstract: An A/D converter and a semiconductor device simple in configuration are provided which can keep a constant noise shaping characteristic without depending on manufacturing variations or a temperature change. A semiconductor device includes a delta-sigma modulator, an input changeover switch, and a control logic circuit. The delta-sigma modulator can change a time constant of an internal circuit according to a control signal. The input changeover switch selectively inputs any one of an input amplitude voltage and a reference voltage to the delta-sigma modulator. A control logic circuit is coupled to an output of the delta-sigma modulator, and generates the control signal.Type: ApplicationFiled: January 26, 2012Publication date: August 9, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki OKADA, Naohiro MATSUI
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Publication number: 20120201111Abstract: An optical disk reproducing device for controlling false detection of synchronization signals due to intersymbol interference, and stably improving accuracy of frequency acquisition of a phase locked loop (PLL) even when offset and so on occur. A signal width close to an original mark length is obtained to use for frequency acquisition of the PLL by, for example, using two different slice thresholds and taking a width between a rising of a result of slicing at one threshold and a falling of a result of slicing at the other threshold as a synchronization signal width. When asymmetric properties due to offset, asymmetry, etc. occur, an amount of corrections on the slice threshold is calculated, and it is reflected on a threshold previously set to always obtain a correct synchronization signal width.Type: ApplicationFiled: April 16, 2012Publication date: August 9, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yusuke Nakamura, Masakazu Ikeda, Koichiro Nishimura
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Publication number: 20120193787Abstract: A rewiring is formed by forming a Cu seed layer of copper over an opening and insulating films, forming a photoresist film over the Cu seed layer, a step of forming copper film by plating-growth over the Cu seed layer, and forming a Ni film. After forming an Au film in an opening (pad region) over the rewiring, the photoresist film is removed and passivation processing is performed on the Ni film. Then, the Cu seed layer other than the formation region of the rewiring is etched. According to these steps, a passivation film is formed on the surface of the Ni film and the reduction in film thickness of the Ni film by the etching can be reduced. Furthermore, it is possible to reduce trouble due to distortion of a substrate resulting from an increase in thickness of the Ni film in view of reduction in film thickness.Type: ApplicationFiled: January 27, 2012Publication date: August 2, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tota MAITANI, Yutaro EBATA
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Publication number: 20120195110Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.Type: ApplicationFiled: April 10, 2012Publication date: August 2, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masanao YAMAOKA, Kenichi OSADA, Kazumasa YANAGISAWA
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Publication number: 20120193728Abstract: A semiconductor device includes a semiconductor substrate, a first gate insulating film, a silicon-containing second gate insulating film, and a first gate electrode. The first gate insulating film is formed on the semiconductor substrate and made of a material having a dielectric constant higher than a dielectric constant of silicon oxide or silicon oxynitride. The silicon-containing second gate insulating film is formed on the first gate insulating film. The first gate electrode is formed on the silicon-containing second gate insulating film and includes a metal nitride layer. The first gate insulating film, the silicon-containing second gate insulating film and the metal nitride layer form part of the pMOSFET.Type: ApplicationFiled: January 5, 2012Publication date: August 2, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Takeo MATSUKI
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Publication number: 20120194265Abstract: The present invention is directed to accurately set a frequency characteristic of a filter integrated in a semiconductor integrated circuit. A semiconductor integrated circuit includes a filter circuit, a cutoff frequency calibration circuit, and a Q-factor calibration circuit. The cutoff frequency calibration circuit adjusts cutoff frequency of the filter circuit to a desired value by adjusting capacitance components of the filter circuit. After adjustment of the cutoff frequency of the filter circuit by the cutoff frequency calibration circuit, the Q-factor calibration circuit adjusts the Q factor of the filter circuit to a desired value by adjusting a resistance component of the filter circuit.Type: ApplicationFiled: January 25, 2012Publication date: August 2, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yusaku KATSUBE, Kosuke TSUIJI, Yutaka IGARASHI, Akio YAMAMOTO
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Publication number: 20120198257Abstract: Timers #0 through #3 are each supplied with a period for prohibiting a change in a power supply voltage. An OS #A or an OS #B determines necessity to change an operating frequency for a CPU core corresponding to any of the timers #0 through #3 when the timer exceeds the prohibition period. It is determined whether it is necessary to change a power supply voltage supplied to CPU cores #0 through #3 when the OS #A or the OS #B determines necessity to change an operating frequency. When it is determined that a power supply voltage needs to be changed, a power supply voltage change portion 20 changes the power supply voltage supplied to the CPU cores #0 through #3. Therefore, it is possible to improve the processing efficiency without needing to acquire inter-OS lock.Type: ApplicationFiled: January 31, 2012Publication date: August 2, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hitoshi YAMAMOTO, Akio IDEHARA, Yasuhiro TAWARA
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Publication number: 20120196555Abstract: The present invention is provided to shorten the period of DC offset cancellation operation. One of terminals of two calibration resistors is connected to the differential output terminals of an active low pass filter having a filter process and an amplification function, and two input terminals of a voltage comparator and two terminals of a switch are connected to the other terminal of the two calibration resistors. In a calculation period of calculating digital control signals for reducing DC offset voltage, the voltage comparator detects calibration voltage depending on a voltage drop of one of the calibration resistors caused by analog current of a digital-to-analog converter. In a calibration period of reducing the DC offset voltage, the calibration analog current of the digital-to-analog converter responding to the digital control signal is passed to the input side of the filter via the switch.Type: ApplicationFiled: January 19, 2012Publication date: August 2, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yutaka IGARASHI, Yusaku KATSUBE
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Publication number: 20120188375Abstract: A semiconductor integrated circuit has a video encoder including a motion prediction unit, a motion compensation unit, a subtraction unit, a discrete cosine transform unit, a quantization unit, an inverse quantization unit, an inverse discrete cosine transform unit, and an addition unit. The encoder divides the video signal from the camera into a plurality of partial images including the central part of the image and the peripheral part of the image according to the distance from the center of the image, and processes the partial images. A pixel processing unit coordinate-transforms coordinates of a pixel included in the central part of the image into coordinates of the peripheral part of the image, and performs a process of enlarging an object of a subject included in the central part of the image on a pixel-by-pixel basis when performing the coordinate transform.Type: ApplicationFiled: January 20, 2012Publication date: July 26, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Yutaka FUNABASHI
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Publication number: 20120187573Abstract: A semiconductor wafer having a plurality of interconnect layers, includes a plurality of chip-composing portions, a dicing region separating the chip-composing portions from each other, and a plurality of inter-chip interconnects formed in the dicing region and electrically connecting adjacent ones of the chip-composing portions, wherein each of the inter-chip interconnects has a width of an intermediate portion narrower than widths of connection end portions connected to the adjacent ones of the chip-composing portions.Type: ApplicationFiled: April 3, 2012Publication date: July 26, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi UCHIDA, Yoshitsugu Kawashima, Hiroshi Ise
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Publication number: 20120188823Abstract: A semiconductor device includes a charge pump circuit that generates a first voltage during a first period and a second voltage during a second period following the first period by a boosting operation, a load current application circuit that includes a first memory cell, and that applies the first voltage to the first memory cell, a memory circuit that includes a second memory cell, and that applies the second voltage to the second memory cell; and a voltage detection circuit that monitors a value of the first voltage to determine whether or not the first voltage is increased to the predetermined voltage, wherein the charge pump circuit stops the boosting operation if the first voltage is less than the predetermined voltage at an end of the first period.Type: ApplicationFiled: April 3, 2012Publication date: July 26, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Yoshitaka SOMA
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Publication number: 20120187532Abstract: A semiconductor device, includes a semiconductor device, a wiring layer provided on the semiconductor substrate, a high frequency wiring provided in the wiring layer, and plural dummy metals provided in the wiring layer apart from the high frequency wiring, wherein the wiring layer in plan view includes a high frequency wiring vicinity region and an external region surrounding the high frequency wiring vicinity region, wherein the high frequency wiring vicinity region includes a first region enclosed by an outer edge of the high frequency wiring, and a second region surrounding the first region, wherein the plural dummy metals are disposed dispersedly in the high frequency wiring vicinity region and in the external region respectively, and wherein an average interval between the dummy metals in the high frequency wiring vicinity region is wider than that in the external region.Type: ApplicationFiled: April 5, 2012Publication date: July 26, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Shinichi UCHIDA
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Publication number: 20120188674Abstract: A load driving device according to an aspect of the present invention may includes an output transistor and a load connected in series between first and second power supply lines, a protection transistor connected between a gate of the output transistor and the second power supply line, the protection transistor turning on the output transistor when a polarity of a power supply connected between the first and second power supply lines is reversed, and a resistor arranged on a line, which supplies a voltage to a back gate of the protection transistor.Type: ApplicationFiled: March 30, 2012Publication date: July 26, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Akihiro Nakahara
