Abstract: A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12. The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4. The source/drain 8 includes nickel silicide 9 on its boundary to the silicon nitride film 10. The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.

Abstract: When a power amplifier mounted in mobile communications equipment, such as a mobile-phone, is composed of a balanced amplifier, technology with which the loss of the electric power composition in a power combiner can be reduced is provided. According to the technical idea of the present embodiment, by dividing an isolation capacitor element into two capacitor elements with high symmetry and coupled in parallel, it is possible to make almost equal parasitic capacitance arising from these capacitor elements, even when the capacitor elements are formed as interlayer capacitor elements of the wiring substrate.

Abstract: Provided is an electronic device of high reliability having an exposed functional portion. An electronic device 10 comprises an electronic element 11 having an exposed functional portion 11a on a first surface, a frame member 12 having a first penetration hole 12a, and a board 13 having a second penetration hole 13a. The frame member 12 is provided on the first surface of the electronic element 11 such that the first penetration hole 12a faces at least a part of the functional portion 11a. The electronic element 11 is mounted on the board 13 such that at least a part of the functional portion 11a faces the second penetration hole 13a. The frame member 12 does not contact with the board 13.

Abstract: In a related transmitting circuit employing electromagnetic induction that is used in a communication system, there is a problem in that, because only one inductor is used in the transmitting circuit, it is impossible to perform communication at a data rate higher than the self-resonant frequency of the inductor. A transmitting circuit according to an embodiment of the present invention is a transmitting circuit that drives an inductor to transmit data to a semiconductor chip insulated from a semiconductor chip on which the transmitting circuit is mounted, and includes a driving circuit that receives outgoing data transmitted at a data rate higher than the self-resonant frequency of the inductor and outputs an outgoing signal that drives the inductor at the data rate of the outgoing data.

Abstract: A high power amplifier used for a front end module of a cellular telephone is a silicon-based CMOS integrated circuit. The output stage of the amplifier includes an LDMOSFET portion in which many LDMOSFET cells are integrated. In the LDMOSFET cell, to reduce the resistance between a backside source electrode and a surface source region, a polysilicon plug doped with boron in a high concentration is embedded into a semiconductor substrate. The polysilicon plug contracts due to solid phase epitaxial growth caused by a heat treatment to generate strain in the silicon substrate. The manufacturing method of a semiconductor device such as an LDMOSFET includes forming a hole passing through an epitaxial layer from the surface of a substrate and embedding a polysilicon plug. A polysilicon member is deposited out in a state where a thin silicon oxide film exists on the inner surface of the hole.

Abstract: In a semiconductor integrated circuit, having a central processing unit, a clock generating unit, an A/D converter and a sample and hold signal generating circuit, noise from an element that operates in accordance with operation timing that is difficult to predict beforehand is reduced. In a calibration operation, in response to a clock signal from the clock generating unit, a sample and hold signal generating circuit supplies a plurality of clock signals sequentially to a sample and hold circuit of the A/D converter. By analyzing a plurality of digital signals that are sequentially output from an A/D conversion circuit of the A/D converter, a timing of a holding period for allowing A/D conversion under a low noise condition is selected from the clock signals. In normal operation, a clock signal selected by the calibration operation is supplied as a sample and hold control signal to the sample and hold circuit.

Abstract: A reduction is achieved in the primary-side input impedance of a transformer (voltage transformer) as an output matching circuit without involving a reduction in Q-factor. An RF power amplifier includes transistors, and a transformer as the output matching circuit. The transformer has a primary coil and a secondary coil which are magnetically coupled to each other. To the input terminals of the transistors, respective input signals are supplied. The primary coil is coupled to each of the output terminals of the transistors. From the secondary coil, an output signal is generated. The primary coil includes a first coil and a second coil which are coupled in parallel between the respective output terminals of the transistors, and each magnetically coupled to the secondary coil. By the parallel coupling of the first and second coils of the primary coil, the input impedance of the primary coil is reduced.

Abstract: A display drive circuit of the invention has: an initial-color-gamut-apex-coordinate-storing unit capable of storing initial color gamut apex coordinates; a user-target-color-gamut-apex-coordinate-storing unit capable of storing user target color gamut apex coordinates; a saturation-expansion-coefficient-deciding unit for deciding expansion coefficients of saturation data based on the initial and user target color gamut apex coordinates; and an expansion unit for expanding saturations of display data based on the saturation expansion coefficients. The expansion coefficients of saturation data are decided based on the initial and user target color gamut apex coordinates, and saturations of display data are expanded according to the expansion coefficients. Thus, the degree of expanding the saturations can be controlled for each color gamut or each of R, G and B color properties of an LC display panel.

Abstract: There is provided a bias circuit including a power amplifier in which influence of variation of a gate length L is reduced and variation of a gain among products is low. Two NPN- and PNP-type current mirror circuits 101 (NPN type) and 102 (PNP type) are inserted on an input side of a bias circuit 103. It is designed that a gate length of a transistor Q1 on an output side of the current mirror circuit 101 is longer than that of the other transistor. In this manner, even when an error is generated, influence of the error can be suppressed to be small.

Abstract: A technology with which the reliability of a package making up a semiconductor device can be enhanced is provided. A feature of the technical idea of the invention is that: a heat sink unit and an outer lead unit are separated from each other: and the outer lead unit is provided with chip placement portions and each of the chip placement portions and each heat sink are joined together. As a result, when a sealing body is formed at a resin sealing step, tying portions function as a stopper for preventing resin leakage and the formation of resin burr in a package product can be thereby prevented. In addition, camber does not occur in the heat sink unit and cracking in a sealing body caused by winding (camber) can be suppressed.

Abstract: A semiconductor device, includes a substrate, an element isolating film formed in the substrate, a first element formation region isolated by the element isolating film, a second element formation region positioned adjacent to the first element formation region and isolated by the element isolating film, a first well of a second conductive type formed in a whole area of the first element formation region, a first transistor of a first conductive type formed on the first element formation region, a second transistor of the first conductive type which is formed on the first element formation region and whose threshold voltage is the same as a threshold voltage of the first transistor, a second well of the second conductive type formed in a whole area of the second element formation region, and a third transistor of the first conductive type formed on the second element formation region.

Abstract: A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.

Abstract: There is provided a radio-frequency module and a radio communication system capable of supporting multiple bands at low cost or small size. A high-frequency power amplifier device includes a power amplifier circuit unit for GSM and a control circuit outputting antenna switch control signals with a VSW1 level or a VSW2 level in response to a mode setting signal for selecting GSM or W-CDMA. The VSW2 level is generated by boosting the VSW1 level using a clock signal from an oscillation circuit. When GSM is selected by the mode setting signal, the high-frequency power amplifier device stops the oscillation circuit and outputs the antenna switch control signals of the VSW1 level to an antenna switch device. When W-CDMA is selected by the mode setting signal, the high-frequency power amplifier device outputs the antenna switch control signals of the VSW2 level to the antenna switch device, using the oscillation circuit.

Abstract: A voltage regulator circuit includes a differential amplifier circuit that includes a first input terminal and a second input terminal, the first input terminal supplied a reference voltage, an output circuit that receives an output voltage from the differential amplifier circuit to generate a first voltage based on the output voltage, and a control circuit that compares the first voltage with a second voltage, and outputs the first voltage or a third voltage to the second input terminal based on a result of comparing, the second and third voltage being different from the first voltage.

Abstract: Miniaturization and high-performance of a semiconductor device are promoted, which has a package on package (POP) structure in which a plurality of semiconductor packages is stacked in a multistage manner. A testing conductive pad for determining the quality of a conduction state of a microcomputer chip and a memory chip is arranged outside a conductive pad for external input/output and thereby the route of a wire that couples the microcomputer chip and the memory chip to the testing conductive pad is reduced in length. Further, the wire that couples the microcomputer chip and the memory chip to the testing conductive pad is coupled to a pad in the outer row among conductive pads in two rows to be coupled to the microcomputer chip.

Abstract: A semiconductor device manufacturing method which improves exposure characteristics. The method includes the step of making preparations for use of an exposure apparatus. The apparatus includes a light emitting unit with a first electrode and a second electrode for generating EUV light, a heating light source for heating the first electrode and the second electrode, and an exposure unit for projecting the EUV light on a substrate through a mask. The method also includes the following steps: heating the first electrode and the second electrode by the heating light source; after the heating step, applying a voltage between the first electrode and the second electrode and generating EUV light by plasma excitation of predetermined atoms; and leading the EUV light into the exposure unit and making an exposure on a photosensitive film formed over the substrate inside the exposure unit.

Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Abstract: There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels.

Abstract: Disclosed is a high-frequency power amplifier device capable of reducing a talk current. For example, the high-frequency power amplifier device has first and second power amplifier circuits, first and second transmission lines, and a region in which the first and second transmission lines are disposed close to each other. Either the first or second power amplifier circuit becomes activated in accordance with an output level. When the second power amplifier circuit is activated, currents flowing in the first and second transmission lines are transmitted in the same direction so that magnetic coupling occurs to strengthen each transmission line's magnetic force. When, on the other hand, the first power amplifier circuit is activated, currents flowing in the first and second transmission lines are transmitted in the opposite directions so that magnetic coupling occurs to weaken each transmission line's magnetic force.

Abstract: A power controller, includes a digital control circuit that outputs a result of comparing a first voltage being input and a voltage reference, and a processor control circuit that stops an operation of the processor based on the result of comparing.