Abstract: An internal operation of RF IC is adjusted so that the level of an RF transmitter signal is substantially stopped from rising, or made to descend in course of ramp-up of the RF transmitter signal. This adjustment is enabled by ramp-up adjustment data Last 4 symbols contained in preamble data precedent to real transmission data transmitted after completion of ramp-up. The ramp-up adjustment data and real transmission data are supplied from a baseband LSI. The RF transmitter signal contains phase and amplitude modulation components according to the EDGE system. RF IC includes phase and amplitude modulation control loops PM LP and AM LP. Ramp-up of RF power amplifiers PA1 and PA2 is performed by controlling the gain of the first variable amplifier MVGA included in the AM LP according to ramp information. Thus, unwanted radiation's level is reduced during ramp-up of the RF transmitter signal of the RF power amplifiers.

Abstract: A power controller, includes a digital control circuit that outputs a result of comparing a first voltage being input and a voltage reference, and a processor control circuit that stops an operation of the processor based on the result of comparing.

Abstract: Disclosed is a high-frequency power amplifier device capable of reducing a talk current. For example, the high-frequency power amplifier device has first and second power amplifier circuits, first and second transmission lines, and a region in which the first and second transmission lines are disposed close to each other. Either the first or second power amplifier circuit becomes activated in accordance with an output level. When the second power amplifier circuit is activated, currents flowing in the first and second transmission lines are transmitted in the same direction so that magnetic coupling occurs to strengthen each transmission line's magnetic force. When, on the other hand, the first power amplifier circuit is activated, currents flowing in the first and second transmission lines are transmitted in the opposite directions so that magnetic coupling occurs to weaken each transmission line's magnetic force.

Abstract: A display panel drive circuit is provided with a first display output terminal to be connected with a data line of a display panel, first and second output stages, and a control circuit. The first output stage is directly connected with the first display output terminal and configured to output a data signal with the positive polarity with respect to a standard voltage level. The second output stage is also directly connected with the first display output terminal and configured to output a data signal with the negative polarity with respect to the standard voltage level. The control circuit controls the first and second output stages so that one of the first and second output stages is selectively activated while the other of the first and second output stages is deactivated.

Abstract: A semiconductor integrated circuit device, includes a first electrode including a first semiconductor layer formed on a substrate, a side surface insulating film formed on at least a part of a side surface of the first electrode, an upper surface insulating film formed on the first electrode and the side surface insulating film, a second electrode which covers the side surface insulating film and the upper surface insulating film, and a fin-type field effect transistor. The first electrode, the side surface insulating film, and the second electrode constitute a capacitor element. A thickness of the upper surface insulating film between the first electrode and the second electrode is larger than a thickness of the side surface insulating film between the first electrode and the second electrode, and the fin-type field effect transistor includes a second semiconductor layer which protrudes with respect to the plane of the substrate.

Abstract: An apparatus includes a display displaying a first map representing a position of the apparatus obtained as a result of a first positioning, and further displaying a second map representing the position of the apparatus and being obtained as a result of a second positioning which is started before displaying the first map, the second map being displayed without responding to a request for displaying the position of the apparatus obtained as a result of the second positioning.

Abstract: A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.

Abstract: A voltage generated in any of a plurality of semiconductor chips is supplied to another chip as a power supply voltage to realize a stable operation of a semiconductor device in which the semiconductor chips are stacked in the same package. For example, two chips are stacked with each other, first to third pads are disposed along corresponding sides of the respective chips, which are arranged close and in parallel to each other, and these pads are commonly connected to each other with first to third metal wires, respectively. In another example, fourth and fifth pads are disposed along a side different from a side along which the first to third pads are disposed, and further connected to each other with a fourth metal wire directly between the chips.

Abstract: The semiconductor device includes a tab including a chip supporting surface, and a back surface opposite to the chip supporting surface; a plurality of suspension leads supporting the tab; a plurality of leads arranged between the suspension leads; a semiconductor chip mounted on the chip supporting surface of the tab, the semiconductor chip including a main surface, a plurality of pads formed on the main surface, and a rear surface opposite to the main surface; a seal portion sealing the semiconductor chip such that a part of each of the leads is exposed from the seal portion; and a Pb-free solder formed on the part of each of the leads. A part of the rear surface of the semiconductor chip is contacted with the seal portion.

Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Abstract: A resistor string type D/A converter includes a higher-order decoder to which a digital signal is input, a higher-order resistor string in which a plurality of resistors and a plurality of voltage drawing points are alternately connected between a first reference voltage and a second reference voltage, the higher-order resistor string being configured to output a plurality of first voltages, each from a respective one of the plurality of voltage drawing points, a plurality of first higher-order switches connected to the plurality of voltage drawing points in a one-to-one configuration, conductive states of the first higher-order switches being controlled based on the digital signal, and a conversion unit that outputs a second voltage based on the plurality of the first voltages supplied through the plurality of first higher-order switches. The higher-order decoder brings two first higher-order switches into conduction based on the digital signal.

Abstract: A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group.

Abstract: A semiconductor device includes a base film, a semiconductor chip mounted on the base film, and a plurality of leads formed on the base film, each of the leads including one end coupled to the semiconductor chip and another end being opposite to the one end. The another end of a first one of the leads and the another end of a second one of the leads are located at different positions respectively between the semiconductor chip and a cut line along which the base film is cut.

Abstract: A DC-DC converter supplies an output voltage to a plurality of channels of a light emitting device array in common. A current driver has a plurality of driver units which drive the channels. Each of the driver units includes a drive transistor and a detector which detects an abnormality of a drive current. A logic unit generates digital data in response to a plurality of detection signals and supplies the same to a D/A converter. An analog reference voltage of the D/A converter is supplied to the DC-DC converter. The logic unit executes a calibration operation which determines digital data for setting the minimum output DC voltage at the normal operation of all the channels by sequential updating of the digital data.

Abstract: A differential amplifier has an interpolating function and has: first and second differential pairs including transistors of a first conductivity type; third and fourth differential pairs including transistors of a second conductivity type; first and second current sources providing operating currents to the first and second differential pairs; third and fourth current sources providing operating currents to the third and fourth differential pairs; a first control circuit which controls, in a first operating range where the amounts of currents flowing through the first and second differential pairs become smaller, respectively, a changing point at which the operating current of the first differential pair changes; and a second control circuit which controls, in a second operating range where the amounts of currents flowing through the third and fourth differential pairs become smaller, respectively, a changing point at which the operating current of the fourth differential pair changes.

Abstract: A solid state imaging device has a semiconductor substrate, a light receiving region provided on a surface layer on a first surface side of the semiconductor substrate, the light receiving region having a silicided surface, second impurity diffusion layer provided adjacent to the light receiving region on the surface layer on the first surface side of the semiconductor substrate, a gate insulating film provided adjacent to the second impurity diffusion layer on the first surface of the semiconductor substrate, a gate electrode provided on the gate insulating film, and a third impurity diffusion layer provided on an opposite side to the second impurity diffusion layer, with the gate insulating film and the gate electrode sandwiched.

Abstract: A differential amplifier includes first and second current paths, each connected between first and second power supplies (PS) and respectively outputting first and second differential output signals. The first current path includes: first transistor, selectively interconnected between the first PS and a first output terminal, its gate receiving one differential input signal; second transistor, connected between the second PS and the first output terminal, its gate receiving the other differential input signal; and first switch circuit. The second current path includes: third transistor, selectively interconnected between the second PS and a second output terminal, its gate receiving one differential input signal; fourth transistor, connected between the first PS and the second output terminal, its gate receiving the other differential input signal; and second switch circuit. One of the first and second switch circuits is connected to the first PS and the other is connected to the second PS.

Abstract: A display panel driver includes a compression circuit configured to, when receiving image data of a plurality of pixels of a target block, generate compressed image data corresponding to the target block by compressing the image data, an image memory configured to store the compressed image data, a decompression circuit configured to generate decompressed image data by decompressing the compressed image data reading from the image memory, and a drive circuit configured to drive a display panel in response to the decompressed image data. The number of bits of the compression type recognition bit of the compressed image data becomes low, when the correlation between the image data of the plurality of pixels becomes low.

Abstract: Provided is a method of manufacturing a semiconductor device, that buried gate electrodes are formed in a pair of trenches in a substrate, so as to be recessed from the level of the top end of the trenches, a base region is formed between a predetermined region located between the pair of trenches, and a source region is formed over the base region.

Abstract: There is provided an EUV exposure apparatus which restrains its optical systems or a mask used therein from being polluted by contaminations generated in its chamber. An energy beam generating source is arranged near a wafer stage set in the chamber of the EUV exposure apparatus to decompose an emission gas generated from a resist painted on the front surface of a wafer by an energy beam. In this manner, lightening mirrors configuring a lightening optical system as one of the optical systems, projection mirrors configuring a projection optical system as another of the optical systems, the mask, and others are protected from being polluted by contaminations.