Abstract: An optically coupled device includes a light emitting element and a light receiving element which are electrically isolated from each other, and an optical waveguide allowing therethrough transmission of light from the light emitting element to the light receiving element, wherein the optical waveguide is covered with an encapsulation resin containing a light reflective inorganic particle which is typically composed of titanium oxide, the light emitting element and the light receiving element are respectively provided on a base (for example, package terminals), and the entire portion of the outer surface of the optical waveguide, brought into contact with none of the light emitting element, the light receiving element and the base, is covered with the encapsulation resin.

Abstract: A higher precision resistive element suppresses variation of the resistance value due to variation of film thickness. A resistive element includes a first portion having a first film thickness and a first width, and a second portion having the first film thickness and a second width determined by the first width. The sum of the first and second widths is constant. The first portion has an upper surface at a position at which a height from the bottom surface of the resistive element first portion is a first height. The resistive element second portion has an upper surface of the resistive element second portion at a position at which a height from a surface including the bottom surface of the resistive element first portion is the first height. The resistive element first portion and the resistive element second portion are coupled to each other via a coupling portion.

Abstract: A power semiconductor device has: an output transistor connected between a power-supply terminal and an output terminal; a gate charge-discharge circuit configured to charge/discharge a first node connected to a gate of the output transistor to ON/OFF control the output transistor; a short switch circuit connected between the first node and the output terminal; and a short control circuit configured to control the short switch circuit. In the turn-ON period, the ON period and the turn-OFF period, the short control circuit cuts off electrical connection between the first node and the output terminal through the short switch circuit. In the OFF period, the short control circuit electrically connects the first node and the output terminal through the short switch circuit.

Abstract: Disclosed is a high-frequency signal processing device capable of reducing transmission power variation and harmonic distortion. For example, the high-frequency signal processing device includes a pre-driver circuit, which operates within a saturation region, and a final stage driver circuit, which operates within a linear region and performs a linear amplification operation by using an inductor having a high Q-value. The pre-driver circuit suppresses the amplitude level variation of a signal directly modulated, for instance, by a voltage-controlled oscillator circuit. Harmonic distortion components (2HD and 3HD), which may be generated by the pre-driver circuit, are reduced, for instance, by the inductor of the final stage driver circuit.

Abstract: For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.

Abstract: The present invention provides a semiconductor device including at least one of an insulating layer and a semiconductor layer each including a hole formed therein, and a through electrode provided in the hole. In the semiconductor device, the side wall of the hole is constituted of a first region from the opening of the hole to a predetermined position between the opening of the hole and the bottom surface of the hole, and a second region from the predetermined position to the bottom surface of the hole. The through electrode includes a seed layer and a plating layer. The seed layer covers the second region and the bottom surface of the hole without covering the first region. In addition, the plating layer covers the seed layer and at least a part of the first region.

Abstract: A timer unit includes a first selector that receives a fixed value and a first enable signal, a second selector that receives the fixed value and a count cycle signal, a third selector that receives an output of the second selector, the count cycle signal, and a second enable signal, a first counter circuit that starts counting in response to an output of the first selector, and that generates the count cycle signal and a first counter circuit output signal indicating that a count value approaches a predetermined value, a second counter circuit that starts counting in response to an output of the third selector, and that generates a second counter circuit output signal, a first output signal generator that receives the first counter circuit output signal and the second counter circuit output signal to generate a first output signal, and a second output signal generator.

Abstract: An input switching device is provided between a plurality of functional blocks (NoC routers or IP) connected to a specific router among a plurality of NoC routers of a NoC system and the specific router. The specific router includes a plurality of first buffers that temporarily store flits from the input switching device. A plurality of second buffers in the input switching device correspond to the respective one of the plurality of functional blocks, and temporarily store the flits from the functional block. A controller selectively sets one of the plurality of first buffers as output destination of the flit stored in each of the second buffers based on a free space of the plurality of first buffers. A distributor outputs the flit stored in each of the second buffers to output destination set for the flit by the controller. In this way, throughput degradation of the NoC system can be prevented.

Abstract: An apparatus and method of manufacture may be provided for a package that can be coupled to a common heat sink without external electrical isolation. The apparatus, for example, can include a semi-conductor die comprising at least one electronic device. The apparatus can also include a frame on which a bottom side of the die is mounted, a bottom side of the frame being configured to attach to a printed circuit board. The apparatus can further include a high thermal conductivity resin molded onto a top side of the die.

Abstract: A semiconductor device for preventing an outer well from being separated by a trench gate electrode from the well of a cell region while suppressing increase in the gate resistance in which buried gate electrodes extending in a direction overlapping a gate contact region extend only before a gate electrode so as not to overlap the gate electrode, the source contact situated between each of the buried gate electrodes is shorter than the buried gate electrode in the vertical direction, the ends of the buried gate electrodes on the side of the gate electrode are connected with each other by a buried connecting electrode disposed before the gate electrode, the buried connecting electrode extends in a direction parallel with the longer side of the semiconductor device, and is not connected to the buried gate electrode on the side of the contact situated adjacent to the contact-side buried gate electrode.

Abstract: A liquid crystal display drive circuit includes first and second buffer circuits, first to fourth switches, and a control signal generation circuit (CSGC). The first buffer circuit drives a first or second data line, and the second buffer circuit drives the second or first data line. Closing the first switch makes the first buffer circuit drive the first data line responsive to a first control signal. Closing the second switch makes the second buffer circuit drive the second data line. Closing the third switch makes the first buffer circuit drive the second data line in responsive to a second control signal. Closing the fourth switch is makes the second buffer circuit drive the first data line. The CSGC generates the first-third control signals for causing respective outputs of the first buffer circuit, and the second buffer circuit to be in high impedance state on the basis of a strobe signal.

Abstract: The present method includes: forming a device isolation region in a substrate dividing the device isolation region into first and second diffusion regions; forming a target film to be processed on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.

Abstract: A back-side illuminated solid-state imaging device includes a photodiode and MOS transistors at a semiconductor substrate. The MOS transistors are formed over the front surface of the semiconductor substrate. The photodiode responds to an incident light applied to the back surface opposite to the front surface of the semiconductor substrate. A charge storing portion, and a first and second transfer gates are formed over the main part of the photodiode and the front surface of the semiconductor substrate located above the vicinity of the main part so as to achieve the global shutter function. Since the irradiation light is incident on the photodiode from the back surface of the semiconductor substrate in back-side illuminated solid-state imaging device, the sensitivity of the photodiode is not reduced even when the first and second transfer gates, and the charge storing portion are formed to achieve the global shutter function.

Abstract: An aspect of the present invention is a cryptographic processing apparatus including a division unit that divides input data into multiple partial data items, the input data being one of plaintext and a round processing result; multiple data holding units that hold the partial data items, respectively; and a combining unit that combines the partial data items held in the multiple data holding units into a single round processing target data item to be subjected to round processing. The division unit selects a storage destination of each partial data item from among the data holding units, and stores each of the partial data items into the storage destination selected. The combining unit combines the partial data items into a round processing target item to reconstruct the input data according to the storage destination of each partial data item selected by the division unit.

Abstract: Miniaturization of a multiphase type power supply device can be achieved. A power supply control unit in which, for example, a microcontroller unit, a memory unit and an analog controller unit are formed over a single chip, a plurality of PWM-equipped drive units, and a plurality of inductors configure a multiphase power supply. The microcontroller unit outputs clock signals each having a frequency and a phase defined based on a program on the memory unit to the respective PWM-equipped drive units. The analog controller unit detects a difference between a voltage value of a load and a target voltage value acquired via a serial interface and outputs an error amp signal therefrom. Each of the PWM-equipped drive units drives each inductor by a peak current control system using the clock signal and the error amp signal.

Abstract: A wobble signal extracting circuit includes: a readout signal generating circuit generating an RF signal by adding first and second detection signals corresponding to reflected light from inside and outside a recording track; a first subtractor generating a push-pull signal by subtracting the first and second detection signals, respectively; a first analog-to-digital converter (ADC) converting the RF signal to digital; a second ADC converting the push-pull signal to digital; a residual RF component generating circuit generating a residual RF signal component equivalent to the RF signal component remaining in the digitized push-pull signal; and a second subtractor generating the wobble signal by subtracting the residual RF signal component from the digitized push-pull signal. The residual RF component generating circuit generates the residual RF signal component so that it may approach the remaining RF signal component based on correlation between the wobble signal and the digitized RF signal.

Abstract: An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer is isolated from the first diffusion layer by way of a device isolator film, and is the same conduction type as the first diffusion layer. The gate wiring is formed as one integrated piece with the gate electrode, and extends over the device isolator film. A common contact couples the gate wiring to the second diffusion layer. The gate electrode is comprised of semiconductor material such as polysilicon that is doped with impurities of the same conduction type as the first diffusion layer. The second diffusion layer is coupled only to the common contact.

Abstract: A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first interconnect, a conductive first plug provided on the upper portion of the Cu silicide layer and connected to the first interconnect, a Cu silicide layer covering the upper portion of the first plug, a first porous MSQ film provided over the side wall from the first interconnect through the first plug and formed to cover the side wall of the first interconnect, the upper portion of the first interconnect, and the side wall of the first plug, and a first SiCN film disposed under the first porous MSQ film to contact with the lower portion of the side wall of the first interconnect and having the greater film density than the first porous MSQ film.

Abstract: A switch circuit with a unit capable of improving a margin voltage without using a negative bias generation circuit is provided. A switch comprising an N-type MOSFET is used for a switch passing a signal to an antenna and a switch comprising a P-type MOSFET is used for a shunt switch grounding a signal. A common control signal is input to the gate terminal of the MOSFET constituting each switch. The inverted signal of this control signal is coupled to a ground terminal of the switch, and thus the potential of the gate terminal of each MOSFET can be set to the ground voltage.

Abstract: A USB (Universal Serial Bus) communication apparatus includes: a driver circuit connected to a USB bus and configured to transmit a packet onto the USB bus for a packet transmission period which is determined based on a transmission request signal from another unit. A receiver control circuit generates a fixation request signal and a generation control signal in response to the transmission request signal. A receiver circuit connected to the USB bus generates a squelch signal showing that the packet is being transmitting onto the USB bus, and stops generating the squelch signal in response to the generation control signal. A line state signal control circuit is configured to output a specific line state signal based on the squelch signal to notify to another unit that the packet is been transmitting onto the USB bus, and to fix the specific line state signal in response to the fixation request signal.