Patents Assigned to RENESAS
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Publication number: 20120001342Abstract: The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS•FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die pad 7D2, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.Type: ApplicationFiled: September 15, 2011Publication date: January 5, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yukihiro SATO, Tomoaki UNO
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Publication number: 20120001608Abstract: According to an embodiment of the invention, an apparatus includes a microprocessor-based pulse-width modulation controller configured to generate a pulse-width modulation signal, and a synchronous converter including a first transistor, a second transistor, a first driver, and a second driver. The apparatus further includes a drive voltage generator configured to generate a drive voltage for the synchronous converter. The drive voltage generator is further configured to generate the drive voltage based on a measured output current and a measured input voltage.Type: ApplicationFiled: July 2, 2010Publication date: January 5, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tetsuo SATO, Jim COMSTOCK, Ryotaro KUDO, Masashi KOYANO
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Publication number: 20110316118Abstract: A semiconductor device includes a substrate including a diffusion region, a device isolation region, an inductor region, and a guard ring region, a guard ring formed on the substrate to be connected to the diffusion region in the guard ring region, an insulating film formed on the substrate, in which the insulating film includes an interconnect, and an inductor formed in the inductor region, in which the guard ring region surrounds the inductor region and the device isolation region.Type: ApplicationFiled: June 24, 2011Publication date: December 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi Uchida, Yasutaka Nakashiba
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Publication number: 20110318900Abstract: A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.Type: ApplicationFiled: September 8, 2011Publication date: December 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Daisuke OSHIDA, Toshiyuki TAKEWAKI, Takuji ONUMA, Koichi OHTO
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Publication number: 20110317501Abstract: A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the internal power-supply voltage from the first power-supply circuit through a first line, a second internal circuit that receives a supply of the internal power-supply voltage from the second power-supply circuit through a second line, an inter-block line that connects the first and second lines to each other, and a control circuit that operates the first and second internal circuits in a predetermined operating cycle, and controls a length of a period during which the first and second internal circuits operate simultaneously.Type: ApplicationFiled: June 10, 2011Publication date: December 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Toshikatsu JINBO
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Publication number: 20110316161Abstract: In an insulating film structure having a barrier insulating film, a via interlayer insulating film, a wiring interlayer insulating film, and a hard mask film stacked in this order on an underlayer wiring, a via hole pattern is formed in the insulating film structure, then a groove pattern is formed in the hard mask film, and a grove is formed in the insulating film structure using this as a mask. According to the prior art, the via side wall is oxidized equally severely in the both processes. The trench side wall is oxidized severely in the via first process according to the prior art, whereas, according to the present invention, the oxidation thereof is suppressed to such an extent that an almost non-oxidized state can be created.Type: ApplicationFiled: September 7, 2011Publication date: December 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroto OHTAKE, Munehiro TADA, Makoto UEKI, Yoshihiro HAYASHI
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Publication number: 20110316137Abstract: The semiconductor device includes a semiconductor chip, a chip mounting portion, a suspension lead, and a plurality of leads. Each of the plurality of leads has a first part and a second part, and the suspension lead has a first part and a second part. The first part of each of the plurality of leads and the suspension lead project from the plurality of side surfaces of the sealing body, respectively. Parts of the side surfaces of the plurality of leads and the suspension lead are exposed from the plurality of side surfaces of the sealing body, respectively. An area of the obverse surface of the first part of the suspension lead is larger than an area of the obverse surface of the first part of each of the plurality of leads in a plan view.Type: ApplicationFiled: September 6, 2011Publication date: December 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki NAKAMURA, Atsushi NISHIKIZAWA, Nobuya KOIKE
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Publication number: 20110316124Abstract: A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect.Type: ApplicationFiled: September 7, 2011Publication date: December 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Masaya KAWANO
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Publication number: 20110316062Abstract: In terms of achieving a reduction in the cost of an antenna switch, there is provided a technology capable of minimizing harmonic distortion generated in the antenna switch even when the antenna switch is particularly formed of field effect transistors formed over a silicon substrate. Between the source region and the drain region of each of a plurality of MISFETs coupled in series, a distortion compensating capacitance circuit is coupled which has a voltage dependency such that, in either of the cases where a positive voltage is applied to the drain region based on the potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, the capacitance decreases to a value smaller than that in a state where the potential of the source region and the potential of the drain region are at the same level.Type: ApplicationFiled: June 2, 2011Publication date: December 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masao KONDO, Masatoshi MORIKAWA, Satoshi GOTO
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Publication number: 20110316052Abstract: In addition to a memory macro region and functional circuit regions on a substrate, a semiconductor integrated circuit device includes a dummy pattern region 40 arranged between the functional circuit regions and between the memory macro region 10 and the functional circuit regions and including a dummy pattern. The dummy pattern has a pattern identical to that of diffusion layers and gate electrodes of a memory cell pattern in a memory cell array region. An area ratio of dummy diffusion layer(s) and dummy gate electrode(s) in the dummy pattern region is equal to or greater than that of the diffusion layers and the gate electrode(s) in the memory cell array region.Type: ApplicationFiled: June 1, 2011Publication date: December 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroshi FURUTA, Takaaki KOBAYASHI, Hirofumi AZUHATA, Tomoya MORITA, Ryuichi OKAMURA, Toshifumi TAKAHASHI
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Publication number: 20110316050Abstract: A semiconductor device with a heterojunction bipolar transistor (HBT) and a field effect transistor (FET) formed over the same substrate; providing improved HBT characteristics and a lowered HBT collector resistance and also satisfactory etching of the FET gate recess, along with low ON-resistance in the FET. The sub-collector layer of a heterojunction bipolar transistor (HBT) is a laminated structure of multiple semiconductor layers, and moreover with a collector electrode formed on a section projecting out from one collector layer. In two of the FET, at least one semiconductor layer on the semiconductor substrate side of the semiconductor layers forming the sub-collector layer of the HBT also serves as at least a portion of a capacitor layer. The total film thickness of the HBT sub-collector layer is 500 nm or more; and the total film thickness of the FET capacitor layer is between 50 nm and 300 nm.Type: ApplicationFiled: June 22, 2011Publication date: December 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: YASUNORI BITO
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Publication number: 20110316582Abstract: A semiconductor chip includes a first power supply line and a second power supply line. A first switch is coupled between the first power supply line and the second power supply line, and a second switch is coupled between the first power supply line and the second power supply line. A circuit is coupled to the second power supply line. A first control signal line is coupled to the first switch, and a second control signal line coupled to the second switch. A logic gate is coupled to the first and the second control signal lines and a terminal is coupled to the logic gate to output a signal to an outside of the semiconductor chip.Type: ApplicationFiled: August 30, 2011Publication date: December 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Yasuhiro Oda
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Publication number: 20110318849Abstract: The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating film and a second insulating film having a first concave portion above the light shielding film in the first region and an interconnect hole having a via hole and a second concave portion in the second region in the second insulating film on the first insulating film, wherein an area of the light shielding film is overlapping an area of the first plurality of concave portions.Type: ApplicationFiled: September 2, 2011Publication date: December 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Hidetaka NAMBU
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Publication number: 20110313700Abstract: There is a need to solve a possible system malfunction when a power supply voltage decreases steeply. To solve this problem, a control method is provided for a voltage detection system having an interrupt mode and a reset mode. First and second detection levels are configured. When a power supply voltage is higher than the first detection level, a latch circuit is placed in a first state to enable the interrupt mode. When the power supply voltage becomes lower than or equal to the first detection level, an interrupt signal is generated to change the latch circuit from the first state to a second state and enable the reset mode. A system reset is issued when the power supply voltage becomes lower than or equal to the second detection level in the reset mode.Type: ApplicationFiled: June 20, 2011Publication date: December 22, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Kyouhei KOUNO, Shinichi NAKATSU, Kazuyo YAMAGUCHI, Kimiharu ETO, Kuniyasu ISHIHARA, Hirotaka SHIMODA, Yuusuke URAKAWA, Seiya INDO
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Publication number: 20110310080Abstract: Provided is a drive circuit including a PDAC and an NDAC that respectively select a positive gray scale voltage and a negative gray scale voltage according to gray scale data, a positive Amp and a negative Amp, an output selection switch that inverts outputs of the positive Amp and the negative Amp, an output switch that makes switching to disconnect an amplifier output from data lines during a switching period, a charge share switch that short-circuits the data lines during the switching period, and data selector circuits that set an amplifier input to a fixed voltage not dependent on a gray scale voltage corresponding to gray scale data for display during the switching period.Type: ApplicationFiled: June 21, 2011Publication date: December 22, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Fumio TONOMURA
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Publication number: 20110309487Abstract: The semiconductor device is high in both heat dissipating property and connection reliability in mounting. The semiconductor device includes a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, the first conductive member being exposed from a first main surface of the resin sealing member, and the second conductive member being exposed from a second main surface opposite to the first main surface of the resin sealing member and also from side faces of the resin sealing member.Type: ApplicationFiled: August 24, 2011Publication date: December 22, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yukihiro Satou, Takeshi Otani, Hiroyuki Takahashi, Toshiyuki Hata, Ichio Shimizu
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Publication number: 20110304033Abstract: A semiconductor package has a semiconductor chip, a lead frame in which a semiconductor chip is mounted on a die pad, and a resin sealing the semiconductor chip and the die pad from an upper surface and a lower surface, the resin has a concave portion disposed at the surface and a concave portion situated inside the concave portion in a plan view.Type: ApplicationFiled: May 18, 2011Publication date: December 15, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Hisanori NAGANO
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Publication number: 20110304388Abstract: Disclosed are a semiconductor integrated circuit device and a wireless communication system that are capable of improving reception sensitivity. The wireless communication system includes, for instance, a first duplexer, a second duplexer, a first low-noise amplifier circuit, and a second low-noise amplifier circuit. A transmission band compliant with a communication standard is split into two segments for use, namely, low- and high-frequency transmission bands. A reception band compliant with the communication standard is split into two segments for use, namely, low- and high-frequency reception bands. The first duplexer uses the low-frequency transmission band and low-frequency reception band as passbands. The second duplexer uses the high-frequency transmission band and high-frequency reception band as passbands.Type: ApplicationFiled: May 24, 2011Publication date: December 15, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Taizo YAMAWAKI, Tomonori TANOUE, Kazuaki HORI
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Publication number: 20110305060Abstract: In a wiring substrate, a double data rate (DDR) memory and a memory controller controlling the DDR memory are mounted. Further, in the wiring substrate, plural equal-length wires connecting the DDR memory and the memory controller are formed. The plural equal-length wires include a differential transmission line, such as a clock wire transmitting a clock signal, which is connected via a common mode choke coil. The differential transmission line may have a wire length shorter than a wire length of another equal-length wire, by a wire length corresponding to delay time of a transmission signal due to the common mode choke coil.Type: ApplicationFiled: June 8, 2011Publication date: December 15, 2011Applicants: RENESAS ELECTRONICS CORPORATION, MURATA MANUFACTURING CO., LTD.Inventors: Takashi ICHIMURA, Takanobu NARUSE, Chiaki FUJII
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Publication number: 20110307851Abstract: A static verification program according to the present invention reads a circuit description and property. In a static verification step, static verification of the circuit description is performed on the basis of the property and the number of states that can be reached and the number of states that is reached are calculated. In a search coverage value calculation step, a search coverage value is calculated on the basis of the number of states that can be reached and the number of states that is reached. In a display step, the search coverage value is displayed in a state in which the search coverage value can be visually checked.Type: ApplicationFiled: June 13, 2011Publication date: December 15, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Masaaki SHIMOOKA
