Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

Abstract: A high frequency signal processing device is capable of carrying out high-accuracy modulation by a PLL circuit. A digital loop is configured in addition to an analog loop having, for example, a phase frequency detector, a charge pump circuit, and a loop filter. A digital calibration circuit is provided which searches for the optimal code set to a capacitor bank upon frequency modulation. Upon the search for the optimal code, a calibration controller first sets a division ratio based on a center frequency to a divider and determines the value of a voltage control signal using the analog loop. Then, the loop filter holds the value of the voltage control signal therein, and a division ratio corresponding to a “center frequency+modulated portion” is set to the divider, thereby operating the digital loop. The optimal code is obtained by a convergent value of the digital loop.

Abstract: An autofocus control circuit, includes a focusing unit determining an in-focus location of a subject image based on a contrast evaluation value of a compressed image data under a first environment, and based on a size of the compressed image data under a second environment.

Abstract: To suppress a short circuit between neighboring wires which is caused when the loop of a wire is formed into multiple stages in a semiconductor device in which a wiring board and one semiconductor chip mounted over a main surface thereof are electrically coupled with the wire. In a semiconductor device in which a chip is mounted on an upper surface of a wiring board and a bonding lead of the wiring board and a bonding pad of the chip are electrically coupled with wires, a short circuit between the neighboring wires is suppressed by making larger the diameter of the longest wire arranged in a position closest to a corner part of the chip than the diameter of the other wires.

Abstract: Provided is a parallel comparison/selection operation apparatus which efficiently executes a search for a maximum value or a search for a minimum value with an index. The parallel comparison/selection operation apparatus includes a vector comparison/selection unit 242 that compares each element included in vector data 1 and vector data 2 for each corresponding element using the vector data 1 and the vector data 2, selects one element of the vector data 1 and the vector data 2 based on the comparison result, and generates vector data 3 including the selected element, and an index vector selection unit 243 that selects one element of an index vector 1 and an index vector 2 based on the comparison result vector using the index vector 1 of the vector data 1, the index vector 2 of the vector data 2, and the comparison result vector to generate and output an index vector 3 including the selected element.

Abstract: A signal line is formed in the a-th layer (a?2) of a multi-layered interconnect layer and a redistribution layer. A plain line is formed in the b-th layer (b<a) of the multi-layered interconnect layer and the redistribution layer and overlaps with the signal line when seen in a plan view. Two coplanar lines that are formed in the c-th layer (b?c?a) of the multi-layered interconnect layer and the redistribution layer, extend in parallel to the signal line when seen in a plan view, and interpose the signal line therebetween. A distance h from the signal line to the plain line is smaller than a distance w from the signal line to the coplanar lines. A power supply line, a ground line, and another signal line are not located within the range of the height equal to the distance w from the signal line above the signal line.

Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film above a semiconductor substrate, forming a wiring to be buried in the first insulating film, forming a protruding portion in an upper surface of the wiring, forming a second insulating film above the first insulating film and the wiring including the protruding portion, planarizing a surface of the second insulating film, forming a third insulating film on the second insulating film whose surface is planarized, forming a lower electrode on the third insulating film, forming a capacitor insulating film on the lower electrode, and forming an upper electrode on the capacitor insulating film.

Abstract: An electric device includes first, second and third selectors. A first node connects to a first input of the first selector, a second node connects to a first input of the second selector, a third node connects to a second input of the first selector, and a fourth node connects to a second input of the second selector. A first switch connects to the first node, and a second switch connects to the second node. A first capacitor connects between the first switch and the third node, and a second capacitor connects between the second switch and the fourth node. A fifth node connects between an output of the first selector and a first input of the third selector, and a sixth node connects between an output of the second selector and a second input of the third selector. An A/D converter connects to an output of the third selector.

Abstract: A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor.

Abstract: A device isolation region is made of a silicon oxide film embedded in a trench, an upper portion thereof is protruded from a semiconductor substrate, and a sidewall insulating film made of silicon nitride or silicon oxynitride is formed on a sidewall of a portion of the device isolation region which is protruded from the semiconductor substrate. A gate insulating film of a MISFET is made of an Hf-containing insulating film containing hafnium, oxygen and an element for threshold reduction as main components, and a gate electrode that is a metal gate electrode extends on an active region, the sidewall insulating film and the device isolation region. The element for threshold reduction is a rare earth or Mg when the MISFET is an n-channel MISFET, and the element for threshold reduction is Al, Ti or Ta when the MISFET is a p-channel MISFET.

Abstract: The semiconductor device includes an insulating film that is formed using a cyclic siloxane having a six-membered ring structure as a raw material; a trench that is formed in the insulating film; and a interconnect that is configured by a metal film embedded in the trench. In the semiconductor device, a modified layer is formed on a bottom surface of the trench, in which the number of carbon atoms and/or the number of nitrogen atoms per unit volume is larger than that inside the insulating film.

Abstract: A lead processing apparatus includes a first die unit, a second die unit that is movable relative to the first die unit, a load transmitting portion that transmits a load to the second die unit, and a stopper mechanism that stops the movement of the second die unit in a direction in which the second die unit approaches the first die unit. The stopper mechanism includes a plurality of stroke stopper pairs each having a first stroke stopper fixed to the first die unit and a second stroke stopper that is fixed to the second die unit and comes into contact with the stopper to stop the movement of the second die unit. The load transmitting portion distributes a load to a plurality of load transmission positions and transmits a press load to the second die unit. Each load transmission position is arranged coaxially with the stroke stopper pair.

Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Abstract: The semiconductor device is formed by forming a first metal film over a first main surface of a semiconductor wafer having a first thickness, performing back grinding to a second main surface of the semiconductor wafer thereby making a second thickness thinner than the first thickness and forming an insulation film pattern having a first insulation film and containing an annular insulation film pattern along the periphery of a second main surface of the semiconductor wafer over the second main surface along the periphery thereof. The second main surface of the semiconductor wafer is bonded to a pressure sensitive adhesive sheet thereby holding the device semiconductor wafer by way of the pressure sensitive adhesive sheet to a dicing frame in a state where the insulation film pattern is present.

Abstract: A method of producing a semiconductor device includes forming, on a first insulating film formed on a substrate, a first groove in an element-forming region to form one of a via and a wiring therein, and a first seal ring groove in a seal ring part, forming one of a via and a wiring in the first groove and a first metal layer in the first seal ring groove, and then removing the metal material in a part exposed to an outside of the first groove and the first seal ring groove, forming a second insulating film on the first insulating film, forming, on the second insulating film, a second groove, and a second seal ring groove in the seal ring part on the first seal ring groove, and forming one of a via and a wiring in the second groove and a second metal layer.

Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Abstract: A diagnosis circuit 1 monitors a watchdog timer 2 and supplies a diagnosis result signal 1 indicating whether a monitoring result is normal or not to a diagnosis circuit 2. A diagnosis circuit 3 monitors a watchdog timer 1 and supplies a diagnosis result signal 3 indicating whether a monitoring result is normal or not to the diagnosis circuit 2. The diagnosis circuit 2 determines that the diagnosis circuit 1 or the watchdog timer 2 is abnormal when the diagnosis result signal 1 does not have a value indicating normal. Further, the diagnosis circuit 2 determines that the diagnosis circuit 3 or the watchdog timer 1 is abnormal when the diagnosis result signal 3 does not have a value indicating normal.

Abstract: A method of manufacturing N-type MOSFET includes: implanting a p-type dopant into in a surface layer of a semiconductor substrate to form a channel region; forming a gate insulating film including High-k material and a gate electrode on said channel region; implanting a p-type dopant into both ends of said channel region in an inner portion of said semiconductor substrate to form halo regions; implanting a p-type dopant into both ends of said channel region in a surface layer of said semiconductor substrate to form extension regions. One of said step of forming said channel region and said step of forming halo regions includes: implanting C into one of said channel region and said halo regions. An inclusion amount of said High-k material is an amount that increase of a threshold voltage caused by said High-k material being included in said gate insulating film compensates for decrease of said threshold voltage caused by said C being implanted.

Abstract: When chip-scale molding system is employed for QFP, the number of semiconductor devices available from a leadframe decreases because cavities each requires a runner portion. This problem can be overcome by employing MAP system, but use of a laminate tape increases the production cost. In through mold system, each cavity needs an ejector pin, which however makes it difficult to place a support pillar. The present application provides a manufacturing method of a semiconductor device by filling, while sandwiching a leadframe between mold dies having a matrix-state cavity group in which cavity columns obtained by linking mold cavities in series via a through gate have been placed in rows, a sealing resin in the cavities. In this method, the matrix-state cavity group has, at the cavity corner portions thereof, a support pillar having a cross-section striding over all the cavities adjacent to the cavity corner portions when viewed planarly.

Abstract: A track-and-hold circuit includes a first sampling circuit that samples an analog input signal, a second sampling circuit that samples the analog input signal, the second sampling circuit and the first sampling circuit being connected in parallel, a first amplifier that amplifies a signal output from the first sampling circuit, and a second amplifier that amplifies a signal output from the second sampling circuit.