Abstract: The semiconductor device has the main surface, the semiconductor substrate having the first impurity region formed on the main surface, the first electrode formed on the main surface having the first impurity region, the insulating film formed on the main surface such that surround the first electrode, the second electrode formed on the insulating film such that spaced apart from the first electrode and annularly surround the first electrode, and the semi-insulating film. The first electrode has the outer peripheral edge portion. The semi-insulating film is continuously formed from on the outer peripheral edge portion to on the second electrode. The outer peripheral edge portion includes the first corner portion. The second electrode has the second corner portion facing the first corner portion. The semi-insulating film on the insulating film is removed between the first corner and the second corner portion.

Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor layer, a first insulating film, and a conductive film. The semiconductor layer is formed on the semiconductor substrate. A first trench reaching the semiconductor substrate is formed within the semiconductor layer. The first insulating film is formed on the inner side surface of the first trench such that a portion of the semiconductor substrate is exposed in the first trench. The conductive film is electrically connected with the semiconductor substrate and formed on the inner side surface of the first trench through the first insulating film. In plan view, a first length of the first trench in an extending direction of the first trench is greater than a second length of the first trench in a width direction perpendicular to the extending direction, and equal to or less than 30 ?m.

Abstract: An image sensor including an ADC circuit receiving pixel data to be supplied in parallel from the a pixel array, outputting a reference signal in accordance with a digital code, comparing the reference signal and the pixel data, and outputting the digital code at which the reference signal and the pixel data have a predetermined relation, the ADC circuit including a ramp-signal generating circuit outputting a ramp signal having a gradient with respect to change of the digital code, the gradient being different between when the digital code is in a first range and when the digital code is in a second range different from the first range and an attenuator receiving the ramp signal to be supplied and outputting the reference signal having a gradient being the same between when the digital code is in the first range and when the digital code is in the second range.

Abstract: Detection transistor MNd flows a detection current IdN to a current path CP1n when an output voltage Vo generated in a load terminal PN1 is than a ground voltage GND. A current mirror circuit CMp1 transfers the detection current IdN flowing in the current path CP1n to a current path CP2a. Detecting resistor element Rd1 converts a mirror current I2a flowing in the current path CP2a to a detection voltage Vd1. A control transistor MNc1 is turned on when the converted detection voltage Vd1 is higher than a predetermined value. Then, the output transistor QO is controlled to be off while the control transistor MNc1 is on.

Abstract: Example implementations include a system of secure decryption by virtualization and translation of physical encryption keys, the system having a key translation memory operable to store at least one physical mapping address corresponding to at least one virtual key address, a physical key memory operable to store at least one physical encryption key at a physical memory address thereof; and a key security engine operable generate at least one key address translation index, obtain, from the key translation memory, the physical mapping address based on the key address translation index and the virtual key address, and retrieve, from the physical key memory, the physical encryption key stored at the physical memory address.

Abstract: A conventional network managing method has a problem that there is a high possibility that a setting error of communication software occurs. According to one embodiment, a non-transitory computer-readable medium including a network managing program is executed in a master apparatus, system information stored in a slave apparatus in advance is read out in a procedure conforming to an SNMP, protocol information in which a communication protocol that can be used by the slave apparatus is described is read out from the slave apparatus by using an object ID described in the system information thus read out, and the protocol information thus read out is referred to start communication with the slave apparatus by executing software corresponding to the communication protocol.

Abstract: Systems and methods for evaluating a set of bounding boxes in a blended image are described. A system can include an integrated circuit configured to obtain expected bounding box data. The expected bounding box data can be based on coordinates data of an image. The integrated circuit can determine target coordinates based on the expected bounding box data. The integrated circuit can receive a blended image including a set of objects and a set of bounding boxes. The integrated circuit can extract pixel values located at the target coordinates in the blended image. The integrated circuit can identify an error relating to the set of bounding boxes based on the extracted pixel values and the expected bounding box data.

Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.

Abstract: Apparatuses and methods for operating a power converter are described. An integrated circuit can be integrated in a high-side driver of a high-side fiend-effect transistor (FET) of the power converter. The integrated circuit can detect a phase node voltage of a power integrated circuit. The integrated circuit can, in response to the phase node voltage being less than a threshold voltage, operate a high-side FET of the power integrated circuit in a constant-current mode. The integrated circuit can, in response to the phase node voltage being greater than the threshold voltage, operate the high-side FET of the power integrated circuit in a constant-voltage mode.

Abstract: Systems and methods for controlling data transaction between master and slave devices are described. A master device can be connected to multiple slave devices that can operate under one of a first, a second, and a third operation modes. The first operation mode can cause the master device to perform data transactions with the multiple slave devices via a network element and the multiple slave devices can be connected to one another via the network element. The second operation mode can disconnect the master device from the multiple slave devices, and multiple agents connected to the multiple slave devices can fulfill the data transactions. The third operation mode can cause the master device to perform data transactions with a first subset of the multiple slave devices via the network element, and can cause the master device to be disconnected from a second subset of the multiple slave devices.

Abstract: In an embodiment, a voltage reference circuit is disclosed that includes a first transistor circuit that is configured to receive an external supply voltage as an input and to output a first voltage and a chopper circuit that is configured to receive a second voltage as an input and to output a voltage reference. The chopper circuit has a breakage threshold. The voltage reference circuit further includes a second transistor circuit that is configured to receive the first voltage as an input and to output the second voltage at a value that is less than or equal to the breakage threshold of the chopper circuit.

Abstract: Apparatuses including multiple selectable circuit elements are described. In an example, an apparatus may include a power supply configured to output a voltage. The apparatus may further include a controller connected to the power supply and a transmission unit connected to the controller. The transmission unit may be configured to output power. The transmission unit may include comprising an inverter connected to the power supply. The inverter may include a high-side switching element. The transmission unit may further include a circuit element a circuit connected to the power supply. The circuit may be configured to select the circuit element. The circuit may include a switch connected between the inverter and the circuit element. The switch and the high-side switching element may be configured to be driven by the voltage outputted by power supply. The controller may be configured to control the power being outputted by the transmission unit.

Abstract: In an embodiment, a wireless power transmitter is disclosed that includes a first field-effect transistor, a second field-effect transistor a coil and an analog front end. The wireless power transmitter is configured to drive the coil based at least in part on activations of the first and second field-effect transistors. The analog front end includes a first driver corresponding to the first field-effect transistor and being configured to control activation of the first field-effect transistor based at least in part on a pulse-width modulation signal and a second driver corresponding to the second field-effect transistor and being configured to control activation of the second field-effect transistor based at least in part on the pulse-width modulation signal.

Abstract: To provide a memory protection circuit and a memory protection method suitable for quick data transfer between a plurality of virtual machines via a common memory, according to an embodiment, a memory protection circuit includes a first ID storing register that stores therein an ID of any of a plurality of virtual machines managed by a hypervisor, an access determination circuit that permits the virtual machine having the ID stored in the first ID storing register to access a memory, a second ID storing register that stores therein an ID of any of the virtual machines, and an ID update control circuit that permits the virtual machine having the ID stored in the second ID storing register to rewrite the ID stored in the first ID storing register.

Abstract: A semiconductor device includes a semiconductor substrate having first and second surfaces, an insulated gate bipolar transistor (IGBT) and a diode formed on the semiconductor substrate, wherein the diode comprises a drift layer of a first conductivity type formed so as to have a first region on the first surface of the semiconductor substrate, a first body layer of a second conductivity type formed so as to have a second region adjacent to the first region at an upper portion of the drift layer, a first floating layer of the second conductivity type formed so as to have a third region adjacent to the first region at an upper portion of the drift layer, a first trench electrode formed in a region adjacent to the first floating layer at an upper portion of the drift layer, and a first control gate formed on top of the first region.

Abstract: Methods, systems, and apparatuses for a single edge nibble transmission (SENT) multi-transmission mode are described. In an example, a system can include a transmitter and a receiver connected to one another. The transmitter may encode an identifier of a device in a synchronization nibble of a SENT signal. The transmitter may transmit the SENT signal with the encoded identifier to the receiver. The receiver may receive the SENT signal from the transmitter. The receiver may decode the identifier of the device from the synchronization nibble of the SENT signal to identify the device.

Abstract: Controllers are provided for providing ports corresponding to Dual Role Powers (DRPs), which may be both the feed side and the receive side, in accordance with the USB Type-C and/or USB Power Delivery standards. The controller includes a control interface for controlling a power management unit for controlling charging and discharging of the secondary battery, a signal transmission module for exchanging a signal with a connection destination via a communication line in the USB cable, and a sequence execution unit. If the power supply from the secondary battery becomes over discharged while the power stored in the secondary battery as the power supply side is being supplied to the connection destination, the sequence execution unit stops the substantial execution of the sequence as the power receiving side unless a predetermined condition is satisfied.

Abstract: The semiconductor device includes an image signal processor, a scaler, and an ROI (Region of Interest) controller. The image signal processor executes image processing including demosaic processing and stores the image after the image processing in memory. The scaler reduces the capture image from the image sensor to generate a reduced entire image and causes the image signal processor to execute image processing on the reduced entire image. The ROI controller cuts out a partial region of the captured image from the image sensor to generate an ROI image and causes the image signal processor to execute image processing on the ROI image.

Abstract: The abnormal power supply voltage detection device has a function of accurately detecting the abnormal voltage in accordance with the characteristics of the semiconductor element for each semiconductor chip. Circuit group for operating the adjustment function has a function of preventing the influence of the power supply voltage of the logic system such as control in the semiconductor product malfunctions becomes abnormal. Furthermore, it has a function of detecting the abnormal voltage of the various power supplies in the semiconductor product. It also has a function to test the abnormal voltage detection function in the normal power supply voltage range during use of semiconductor products.

Abstract: A Semiconductor device includes an insulating layer, an optical waveguide, a first dummy semiconductor film, a second semiconductor film and a third semiconductor film. The optical waveguide is formed on the insulating layer. The first dummy semiconductor film is formed on the insulating layer and is spaced apart from the optical waveguide. The first dummy semiconductor film is formed on the first semiconductor film. The second semiconductor film is integrally formed with the optical waveguide as a single member on the insulating layer. The third semiconductor film is formed on the second semiconductor film. A material of the first dummy semiconductor film is different from a material of the optical waveguide. In plan view, a distance between the optical waveguide and the first dummy semiconductor film in a first direction perpendicular to an extending direction of the optical waveguide is greater than a thickness of the insulating layer.