Patents Assigned to RENESAS
  • ADAPTIVE FILTERING FOR PRECISION TIME PROTOCOL WITH PHYSICAL LAYER SUPPORT
    Publication number: 20230291490
    Abstract: Systems and methods for reducing phase delay variation impact are described. A microcontroller can receive a sequence of phase offsets determined by a slave device over time. The microcontroller can determine a weight vector based on a metric associated with the sequence of phase offsets. The microcontroller can adjust a set of filter coefficients based on the weight vector. The set of filter coefficients can be filter coefficients of a filter being implemented by the slave device to filter incoming packet data.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 14, 2023
    Applicant: Renesas Electronics America Inc.
    Inventors: Oleksandr KOROVIN, Alexandru MIHUT, Greg Anton ARMSTRONG, Leonid GOLDIN
  • CALIBRATION AND SYNCHRONIZATION OF GROUND CURRENT SENSING AMPLIFIER WITH WIRELESS POWER TRANSMITTER CONTROLLER
    Publication number: 20230291365
    Abstract: Systems and methods for calibrating a wireless power transmitter is described. A wireless power transmitter can include a controller and an amplifier module. The amplifier module can include an amplifier configured to amplify a voltage converted from a current proportional to power consumed by a wireless power transmitter, and a circuit connected to the amplifier. The circuit can be configured to receive a control signal from the controller. The circuit can be further configured to perform time division multiplexing on an output of the amplifier according to the control signal. A time division multiplexed output of the amplifier can include calibration data of the amplifier. The amplifier can be configured to output the time division multiplexed output to the controller.
    Type: Application
    Filed: March 10, 2022
    Publication date: September 14, 2023
    Applicant: Renesas Electronics America Inc.
    Inventors: Gustavo James MEHAS, Marcin Kamil AUGUSTYNIAK, Giovanni FIGLIOZZI
  • Semiconductor device
    Patent number: 11756605
    Abstract: A semiconductor device capable of decreasing a jitter component is provided. A first calibration circuit searches a second delay value of a data delay circuit while determining a delay value of a strobe delay circuit to be a first delay value that is larger than the minimum value and smaller than the maximum value. A second calibration circuit determines a first corrected delay value and a second corrected delay value by shifting both the first delay value and the second delay value by the same correction value in a direction toward the minimum value, and sets the first corrected delay value and the second corrected delay value to the strobe delay circuit and the data delay circuit, respectively.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: September 12, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Norihiro Saitou
  • Semiconductor device
    Patent number: 11756881
    Abstract: A semiconductor device includes: a first substrate; a multilayer wiring layer formed on the first substrate; a first inductor formed into a meander shape on the multilayer wiring layer in a plan view; and a second inductor formed into a meander shape on the multilayer wiring layer in a plain view, and arranged so as to be close to the first inductor in a plan view and not to overlap with the first inductor. A transformer is configured by the first inductor and the second inductor and, in a plan view, the first inductor and the second inductor extend along a first direction in which one side of the first substrate extends.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: September 12, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Uchida, Yasutaka Nakashiba, Shinichi Kuwabara
  • Active measurement correction of resistive sensors
    Patent number: 11747379
    Abstract: In an embodiment, an apparatus is disclosed that comprises a plurality of resistors arranged as a reverse bridge and configured to convert an input voltage to a scaled output voltage. The scaled output voltage is scaled to a target format based at least in part on a range of the input voltage and a fixed value of the plurality of resistors. The input voltage is generated based at least in part on at least one signal generated by a sensor based at least in part on a measurement of a property of a measurement target. At least one of the plurality of resistors has a resistance value of R and at least another of the plurality of resistors has a resistance value of R plus or minus ?R.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: September 5, 2023
    Assignee: Renesas Electronics America, Inc.
    Inventor: David Mitchell Grice
  • Over-temperature protection circuit
    Patent number: 11750186
    Abstract: An over-temperature protection circuit is described. The circuit comprises an input for sensing a voltage across a transistor, a voltage-to-current converter configured to generate a current in dependence upon the voltage, an accumulator storing a value indicative of power dissipated by the transistor and which depends on the current; and a comparator configured to determine whether the value exceeds a threshold value and, in dependence on the value exceeding the threshold value, to generate a signal to cause the transistor to be switched off.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: September 5, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hans-Juergen Braun
  • Semiconductor device and decoding methods
    Patent number: 11750210
    Abstract: The present invention is to reduce detection of an erroneous edge caused by variation in a case of a sampling frequency that is not larger than a data transmission frequency. A semiconductor device includes: a data reception circuit configured to receive first data at first time and receive second data at second time; and an edge recognition circuit configured to set a range and detect an edge contained in the range. The edge recognition circuit includes a measurement circuit configured to measure a first period taken from the reception of the first data to the reception of the second data, and is configured to determine the range in which the edge contained in the data that is received by the data reception circuit is detected, on the basis of the first period.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: September 5, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koichi Ishimi, Akio Fujii
  • Semiconductor device
    Patent number: 11749597
    Abstract: A semiconductor device comprises a wiring substrate and a semiconductor chip. In the wiring substrate, a plurality of micro-elements each comprised of a stacked structure including a power supply pattern and a ground pattern is arranged at a predetermined interval. In each of the plurality of micro-elements, the power supply pattern is formed in a wiring layer located one layer above or one layer below a wiring layer in which the ground pattern is formed. A power supply potential is to be supplied to the power supply patter, and a ground potential is to be supplied to the ground patter.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: September 5, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Ryuichi Oikawa
  • Semiconductor device
    Patent number: 11747883
    Abstract: A semiconductor device includes clock adjustment circuits, provided to a plurality of functional circuits operating in synchronization with a clock signal respectively for adjusting a delay amount for each functional circuit, and a clock path selection circuit for controlling whether a clock is transmitted to the functional circuits through any one of a plurality of paths included in the clock adjustment circuits respectively. In the semiconductor device, the clock path selection circuit outputs a path instruction signal for instructing switching of a path for transmitting a clock signal in accordance with a change in an operation state of a plurality of functional circuits.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: September 5, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Daisuke Wakasa, Kazuaki Gemma
  • WIRELESS POWER TRANSMITTER IMPLEMENTING MULTIPLEXING FOR MONITORING CIRCUITRY IN A SEMICONDUCTOR DEVICE
    Publication number: 20230275619
    Abstract: In an embodiment, a semiconductor device is disclosed that comprises a multiplexer. The multiplexer is configured to receive signals from each of a plurality of transmission coils of a wireless power transmitter as inputs and to output an output signal based at least in part on one of the signals. The semiconductor device further comprises an attenuator connected to the multiplexer that is configured to adjust a voltage of the output signal. The attenuator comprises a variable resistance. The semiconductor device further comprises a plurality of pull down circuits each corresponding to one of the transmission coils. The pull down circuits are configured to selectively clamp the signals received from the corresponding transmission coils to ground.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 31, 2023
    Applicant: Renesas Electronics America Inc.
    Inventors: Gustavo James MEHAS, Giovanni FIGLIOZZI
  • Semiconductor device and method of manufacturing the same
    Patent number: 11742199
    Abstract: First, an offset spacer including a stacked film of insulating films is formed on the upper surface of the semiconductor layer, the side surface of the gate electrode, and the side surface of the cap film. Next, a part of the insulating films is removed to expose the upper surface of the semiconductor layer. Next, in a state where the side surface of the gate electrode is covered with the insulating films, an epitaxial layer is formed on the exposed upper surface of the semiconductor layer. Here, among the offset spacers, the insulating film which is a silicon nitride film is formed at a position closest to the gate electrode, and the position of the upper end of the insulating film formed on the side surface of the gate electrode is higher than the position of the upper surface of the gate electrode.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: August 29, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuhiko Segi
  • Method of manufacturing semiconductor device
    Patent number: 11740259
    Abstract: An inspection terminal provided in a test device has a main body portion including a support portion that is curved; a plate-shaped portion integrally connected to the support portion and extending in a first direction; a tip portion integrally connected to the plate-shaped portion and having a larger dimension in a second direction intersecting with the first direction than that of the plate-shaped portion in the second direction; and a slit formed from the tip portion to the plate-shaped portion so as not to reach the support portion of the inspection terminal. The tip portion of the inspection terminal has a first contact portion and a second contact portion that are separated from each other by way of via the slit, and each contact portion is brought into contact with an external terminal of a semiconductor package, and an electrical test of the semiconductor package is performed.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: August 29, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Toshitsugu Ishii
  • Semiconductor device
    Patent number: 11742356
    Abstract: Reduction in power consumption of a semiconductor device is achieved. The semiconductor device includes: a first circuit operating at a first power supply voltage and a second circuit operating at a second power supply voltage and including a level shift unit and a switch unit, the first circuit is configured of a low-breakdown-voltage n-type transistor that is an SOTB transistor, and the switch unit is configured of an n-type transistor that is an SOTB transistor. A second power supply voltage is higher than a first power supply voltage, and an impurity concentration of a channel formation region of the n-type transistor is higher than an impurity concentration of a channel formation region of the low-breakdown-voltage n-type transistor.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: August 29, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuya Uejima, Kazuhiro Koudate
  • Semiconductor device and power management IC
    Patent number: 11742336
    Abstract: Semiconductor device has a regulator circuit having an even number of switching regulators that generate output power from an input power supply and a power management IC that controls the output potential generated by the switching regulator. semiconductor device is characterized in that a group of half of the even number of switching regulators is arranged on a first surface of semiconductor device system board, and a group of switching regulators, which is the remaining half, is arranged on a second surface that is in front-back relation with the first surface. This semiconductor device reduces semiconductor device board-area (pattern-resource).
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: August 29, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takafumi Betsui
  • Method of manufacturing semiconductor device
    Patent number: 11742413
    Abstract: Reliability and performance of a semiconductor device are improved. First, a first mask pattern is formed on the semiconductor substrate in each of first to third regions. Next, a second mask pattern made of a material that is different from a material configuring the first mask pattern is formed on a side surface of the first mask pattern and on the semiconductor substrate in each of the first to third regions. Next, by an anisotropic etching process performed to the semiconductor substrate, a plurality of fins protruding from the recessed upper surface of the semiconductor substrate are formed. In the manner, fins each having a different structure from that of a fin in the first region can be formed in the second and third regions.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: August 29, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Atsushi Yoshitomi
  • PHASE DEMODULATION USING PULSE SIGNAL
    Publication number: 20230269117
    Abstract: Systems and methods for phase demodulation is described. A wireless power transmitter can include a controller, a transmission coil, and an integrated circuit connected to the controller and the transmission coil. The integrated circuit can be configured to measure a voltage of a transmission coil of a wireless power transmitter. The integrated circuit can be further configured to generate, based on the measured voltage, a pulse signal comprising a plurality of pulses. The integrated circuit can be further configured to send the pulse signal to the controller of the wireless power transmitter. The controller can be configured to perform phase demodulation using the pulse signal.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Applicant: Renesas Electronics America Inc.
    Inventors: Gustavo James MEHAS, Giovanni FIGLIOZZI, Xintian SHI, Francesco SANTORO
  • Window comparator structure for low power hysteretic buck-boost DC-DC controller
    Patent number: 11736011
    Abstract: The present embodiments relate generally to power controllers, and more particularly to synthetic current hysteretic control of a buck-boost DC-DC controller. In one or more embodiments, a controller includes PFM-PWM and Buck-Boost transitions with minimal circuitry and power consumption. In these and other embodiments, a window comparator structure is provided that is capable of generating control signals for use in buck, boost and buck-boost modes of operation.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 22, 2023
    Assignee: Renesas Electronics America Inc.
    Inventor: Gwilym Francis Luff
  • Method and system for generating and accessing guard services for secure services and operations thereof
    Patent number: 11734414
    Abstract: Example implementations include generating a guard service for a secure service at a secure region of a processing system by detecting a call to a secure service at a secure region of a processing device, obtaining a secure interface associated with the secure service, generating a guard interface based at least partially on the secure interface, generating a guard service based at least partially on the guard interface, locating the guard service at a secure region, and locating the guard interface at a secure address at the secure region.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 22, 2023
    Assignee: Renesas Electronics Corporation
    Inventors: Kimberly Dinsmore, Brandon Hussey
  • SEMICONDUCTOR DEVICE AND IMPEDANCE-MATCHING CIRCUITRY
    Publication number: 20230261679
    Abstract: A semiconductor device includes: a first terminal connected to an antenna; a second terminal connected to an input terminal of a receiving circuitry; a third terminal connected to an output terminal of a transmitting circuitry; a first inductor arranged in a signal path extending from the first terminal to the second terminal; and a second inductor arranged in a signal path extending from the first terminal to the third terminal, and the first inductor and the second inductor are formed so as to have at least a partial overlapping portion in plan view.
    Type: Application
    Filed: February 16, 2023
    Publication date: August 17, 2023
    Applicant: Renesas Electronics Corporation
    Inventors: Kyoya Takegawa, Kenichi Shibata, Hiroaki Matsui
  • Position sensor system, particularly for detecting rotary movement and method for detecting errors in a position sensor system
    Patent number: 11725964
    Abstract: A rotary movement position sensor is presented that includes a first sensor output, a second sensor output, a first signal processing unit, a second signal processing unit, a first system output providing the output of the first signal processing unit or of the second signal processing unit, and a second system output providing the output of the second signal processing unit or of the first signal processing unit. A swapping unit that swaps the first signal processing unit between the first sensor output and first system output to the second sensor output and second system output and simultaneously swaps the second signal processing unit from the second sensor output and second system output to the first sensor output and first system output and vice versa. A method for detecting errors in a position sensor system is also presented.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: August 15, 2023
    Assignee: Renesas Electronics America Inc.
    Inventors: Josef Janisch, Marcin Augustyniak, Angel Karachomakov