Patents Assigned to RENESAS
  • Patent number: 11710695
    Abstract: A semiconductor device has a substrate, a first circuit, a first inductor, a second circuit and a second inductor IND2. The substrate includes a first region and a second region, which are regions different from each other. The first circuit is formed on the first region. The first inductor is electrically connected with the first circuit. The second circuit is formed on the second regions. The second inductor is electrically connected with the second circuit and formed to face the first inductor. A penetrating portion is formed in the substrate. The penetrating portion is formed such that the penetrating portion surrounds one or both of the first circuit and the second circuit in plan view.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: July 25, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasutaka Nakashiba
  • Patent number: 11709787
    Abstract: Apparatuses for controlling data transaction between master and slave devices are described. A master port connected to a master device can include a voltage regulator, a bridging circuit connected to a network element, and a redriver circuit. In response to a data transaction corresponding to a first type of data transaction, the master port can activate the voltage regulator and deactivate the redriver circuit to support a first operation mode causing the master device to perform the data transaction with a slave device via the network element. In response to the data transaction corresponding to a second type of data transaction, the master port can deactivate the voltage regulator and activate the redriver circuit to support a second operation mode causing the master port to disconnect from a slave port connected to the slave device and the data transaction is fulfilled by a circuit connected to the slave device.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: July 25, 2023
    Assignee: Renesas Electronics America, Inc.
    Inventors: Shubing Zhai, James Wang, Jankin Hu, Wei Wang
  • Publication number: 20230231407
    Abstract: Provided is a semiconductor device capable of stably estimating an internal temperature of a battery. A semiconductor device coupled to a battery calculates entropy heat of the battery at a predetermined time by using a charging current of the battery and an internal temperature of the battery at a time before a predetermined time, calculates a heat generation amount of the battery from the charging current of the battery, calculates a heat radiation amount of the battery based on a temperature difference between the internal temperature at the time before the predetermined time and a surface temperature of the battery, and estimates an internal temperature of the battery at the predetermined time by using the entropy heat, the heat generation amount and the heat radiation amount.
    Type: Application
    Filed: December 27, 2022
    Publication date: July 20, 2023
    Applicant: Renesas Electronics Corporation
    Inventors: Masaki HOGARI, Masaru MIYAKE, Yasuo USUDA, Youhei KENGOYAMA, Tetsuo MIYAUCHI
  • Publication number: 20230231502
    Abstract: A method and position sensor system for detecting an error of a position sensor system are provided. The method and position sensor system implementing the steps of: determining the period length of three previous signal periods of the position signal, comparing the period lengths of the three previous signal periods of the position signal to detect a constant velocity position signal, a constant accelerating or decelerating position signal or position signal with a constant jerk, predicting the period length of the next signal period of the position signal, transferring the predicted period length of the next signal period to a predicted position signal for the next signal period, and comparing the predicted position signal with the actual position signal to detect errors in the position signal of the next signal period.
    Type: Application
    Filed: January 17, 2023
    Publication date: July 20, 2023
    Applicant: Renesas Electronics America Inc.
    Inventor: Josef Janisch
  • Patent number: 11705344
    Abstract: A technique capable of shortening process time for plasma cleaning is provided. A method of manufacturing a semiconductor device includes a step of preparing a substrate including a plurality of device regions each including a semiconductor chip electrically connected to a plurality of terminals formed on a main surface by a wire, a step of delivering the substrate while emitting plasma generated in atmospheric pressure to the main surface of the substrate, a step of delivering the substrate while capturing an image of a region of the main surface of the substrate and a step of forming a sealing body by sealing the semiconductor chip and the wire with a resin.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: July 18, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masakatsu Suzuki, Haruhiko Harada, Yasuhiko Akaike
  • Patent number: 11705361
    Abstract: Gate patterns are formed on a semiconductor layer and a conductive film is formed on the semiconductor layer so as to cover the gate patterns. By performing a polishing process to the conductive film and patterning the polished conductive film, pad layers are formed between the gate patterns via sidewall spacers.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: July 18, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hitoshi Maeda, Tatsuyoshi Mihara, Hiroki Shinkawata
  • Patent number: 11705433
    Abstract: A semiconductor device includes a first semiconductor chip, an adhesive layer that is formed on the first semiconductor chip, and a second semiconductor chip that is arranged on the first semiconductor chip via the adhesive layer. The first semiconductor chip has a first semiconductor substrate and a first wiring layer. The first wiring layer has a first inductor and a first electrode pad. The first wiring layer is formed on the first semiconductor substrate. The second semiconductor chip has a second wiring layer and a second semiconductor substrate. The second wiring layer is formed on the first wiring layer via the adhesive layer. The second semiconductor substrate is formed on the second wiring layer, and has a first opening. In a plan view, the first electrode pad is formed so as not to overlap with the second semiconductor chip, and a second electrode pad overlaps with the first opening.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: July 18, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasutaka Nakashiba
  • Publication number: 20230221149
    Abstract: An inductive position sensor and method for detecting a movement of a conductive target, having: at least a first and a second transmitter coil having the same shape and which are phase-shifted to each other, at least one oscillator for generating a first and a second transmitter signal having the same shape and which are phase shifted to each other and are applied to the first transmitter coil and second transmitter coil respectively, at least one receiver coil, and a processing unit for determining a phase-shift between the first or second transmitter signal and a receiver signal received at the receiver coil; the determined phase-shift corresponding to the position of the conductive target above the first and second transmitter coils.
    Type: Application
    Filed: December 6, 2022
    Publication date: July 13, 2023
    Applicant: Renesas Electronics America Inc.
    Inventors: Josef Janisch, Rudolf Pichler, Juergen Kernhof, Svilen Kastev
  • Patent number: 11699645
    Abstract: A semiconductor device includes a wiring substrate having: a first wiring layer having pads; and a second wiring layer having wirings and via-lands. The via-lands include: first-row via-lands connected to first-row pads of the pads, respectively; and second-row via-lands connected to the second-row pads of the pads, respectively. In the perspective plan view, the first-row via-lands have: first via-lands arranged such that a center of each of the first via-lands is shifted in a direction away from a first side of the semiconductor chip than a position overlapping with a center of the corresponding first-row pad; and second via-lands arranged such that a center of each of the second via-lands arranged at a position closer to the first side than the first via-land. In the perspective plan view, the first and second via-lands are alternately arranged in a first direction along the first side.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: July 11, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keita Tsuchiya, Shuuichi Kariyazaki
  • Publication number: 20230216342
    Abstract: In an embodiment, a wireless power transmitter is disclosed that includes a first field-effect transistor, a second field-effect transistor a coil and an analog front end. The wireless power transmitter is configured to drive the coil based at least in part on activations of the first and second field-effect transistors. The analog front end includes a first driver corresponding to the first field-effect transistor and being configured to control activation of the first field-effect transistor based at least in part on a pulse-width modulation signal and a second driver corresponding to the second field-effect transistor and being configured to control activation of the second field-effect transistor based at least in part on the pulse-width modulation signal.
    Type: Application
    Filed: December 31, 2021
    Publication date: July 6, 2023
    Applicant: Renesas Electronics America Inc.
    Inventors: Gustavo James MEHAS, Tae Kwang PARK, Giovanni FIGLIOZZI
  • Publication number: 20230216411
    Abstract: Methods and systems for performing current sense compensation for one or more power stages in a multiphase voltage regulator are described. A controller can be connected to a plurality of power stages through a communication interface. The controller can generate a data packet including a command to obtain temperature information and an address that identifies a specific power stage among the plurality of power stages. The controller can send the data packet to the plurality of power stages using the communication interface. The controller can receive temperature information of the specific power stage from the specific power stage through the communication interface. The controller can compensate a sensed current of the specific power stage based on the received temperature information of the specific power stage.
    Type: Application
    Filed: December 31, 2021
    Publication date: July 6, 2023
    Applicant: Renesas Electronics America Inc.
    Inventors: Robert Thomas GRISAMORE, David Lynn BECK, Kiran GONSALVES, Nicholas John HAVENS
  • Publication number: 20230213954
    Abstract: Methods and systems for operating a voltage regulator are described. An apparatus may receive a feedback signal from a power stage. The feedback signal may be one of a sensed signal measured from an output of the power stage and a calibration signal representing a fixed voltage. The apparatus may convert the feedback signal into a correction signal. The apparatus may further adjust a synthetic current using the correction signal, the synthetic current being associated with the power stage.
    Type: Application
    Filed: December 31, 2021
    Publication date: July 6, 2023
    Applicant: Renesas Electronics America Inc.
    Inventors: Travis John Guthrie, Timothy William Nutt, Aaron Michael Shreeve, Narendra Babu Kayathi, Robert Thomas Grisamore, Kiran Gonsalves
  • Publication number: 20230216791
    Abstract: A system including a controller and a plurality of power stages is described. The system can include a communication interface, the plurality of power stages, and a controller connected to the plurality of power stages through the communication interface. The controller can generate a data packet including a command encoding a task and an address identifying at least one power stage among the plurality of power stages. The controller can send the data packet to the plurality of power stages through the communication interface. Each power stage among the plurality of power stages can receive the data packet through the communication interface, compare the address in the data packet with an address assigned to the power stage, determine whether to perform the task based on a result of the comparison between the address in the data packet with an address assigned to the power stage.
    Type: Application
    Filed: December 31, 2021
    Publication date: July 6, 2023
    Applicant: Renesas Electronics America Inc.
    Inventors: Robert Thomas GRISAMORE, Kiran GONSALVES, James Robert TOKER
  • Patent number: 11695012
    Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: July 4, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takaaki Tsunomura, Yoshiki Yamamoto, Masaaki Shinohara, Toshiaki Iwamatsu, Hidekazu Oda
  • Patent number: 11695014
    Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at most 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: July 4, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryuta Tsuchiya, Toshiaki Iwamatsu
  • Patent number: 11695010
    Abstract: Wells formed in a semiconductor device can be discharged faster in a transition from a stand-by state to an active state. The semiconductor device includes an n-type well applied, in an active state, with a power supply voltage and, in a stand-by state, with a voltage higher than the power supply voltage, a p-type well applied, in the active state, with a ground voltage and, in the stand-by state, with a voltage lower than the ground voltage, and a path which, in a transition from the stand-by state to the active state, electrically couples the n-type well and the p-type well.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: July 4, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Akira Tanabe
  • Patent number: 11687357
    Abstract: In a virtualization system that includes a hypervisor that performs OSID management for linking a plurality of OSs with resources, a guest OS that receives an initial value from the hypervisor and sets a OSID for each resource, and a OSID manager that sets a OSID for each resource, a new OSID created by OSID generator in OSID manager after a certain period of time has elapsed after setting the initial value is set to the guest OS and the IP (resource), and is requested to be updated to a new OSID set by the update controller in OSID manager. This enables simultaneous updating of OSID of the guest operating system and the resources, thus achieving high robustness.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: June 27, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Shibayama, Nhat Van Huynh, Katsushige Matsubara, Seiji Mochizuki
  • Patent number: 11689042
    Abstract: Example implementations include obtaining charging power from a power source, obtaining a charging command, activating a trickle current to a battery, entering a first charging state in response to a condition that a voltage of the battery does not satisfy a deep discharge threshold, and entering a second charging state in response to a condition that a voltage of the battery satisfies a deep discharge threshold. Example implementations can further include supplying the trickle current in a burst to the battery in response to a condition that the voltage of the battery does not satisfy a fuel gauge threshold, upon entering the second charging state. Example implementations can further include supplying the trickle current continuously to the battery in response to a condition that the voltage of the battery satisfies the fuel gauge threshold, upon entering the second charging state.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: June 27, 2023
    Assignee: Renesas Electronics America Inc.
    Inventors: Zhigang Liang, Byongho Park, Mehul Shah
  • Patent number: 11687261
    Abstract: A semiconductor device for achieving consistency of data is provided. The process performed by the semiconductor device includes a step of compressing data to generate compression information representing compressed data and the amount of information, a step of accessing management data for controlling access to a memory area, a step of permitting writing to a memory area in units of a predetermined data size based on the fact that the management data indicates that the accessed area is not exclusively allocated to another compression/expansion module, a step of writing data to update management data, a step of permitting reading from the area in units of the data size based on the fact that the management data indicates that the accessed area is not exclusively owned to another compression/expansion module, and a step of reading the compressed data and the compressed information from the area in units of the data size.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: June 27, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Katsushige Matsubara, Seiji Mochizuki
  • Publication number: 20230198469
    Abstract: Apparatuses and systems implementing an amplifier module are described. The amplifier module can include a substrate. A driver amplifier die, a splitter network, an output amplifier die, a bias controller, and a combiner network can be coupled to the substrate. The driver amplifier die can be configured to receive an input radio frequency (RF) signal. The splitter network can be configured to split an intermediate RF signal outputted from the driver amplifier die into first and second RF signals. The output amplifier die can be configured to receive the first and second RF signals. The bias controller can be configured to bias the driver amplifier die and the output amplifier die. The combiner network can be configured to combine first and second outputs of the output amplifier die to generate an output RF signal and terminate at least one harmonic of the output amplifier die's output impedance.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Applicant: Renesas Electronics America Inc.
    Inventors: Hussain Hasanali LADHANI, Ramanujam SRINIDHI EMBAR