Patents Assigned to RENESAS
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Patent number: 11194491Abstract: A semiconductor device for achieving consistency of data is provided. The process performed by the semiconductor device includes a step of compressing data to generate compression information representing compressed data and the amount of information, a step of accessing management data for controlling access to a memory area, a step of permitting writing to a memory area in units of a predetermined data size based on the fact that the management data indicates that the accessed area is not exclusively allocated to another compression/expansion module, a step of writing data to update management data, a step of permitting reading from the area in units of the data size based on the fact that the management data indicates that the accessed area is not exclusively owned to another compression/expansion module, and a step of reading the compressed data and the compressed information from the area in units of the data size.Type: GrantFiled: November 14, 2019Date of Patent: December 7, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Katsushige Matsubara, Seiji Mochizuki
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Patent number: 11196416Abstract: The invention relates to an inductive proximity switch. The object of the invention to present a very simplified inductive position sensor, which can be reliably used for detecting a zero crossing of its output voltage when a target moves by will be solved by an inductive proximity switch comprising a transmitter coil, a receiver coil, an integrated circuit for excitation of the transmitter coil and a signal processing unit for processing a received signal from the receiver coil, wherein an oscillator excites a resonant circuit comprising the transmitter coil and a parallel capacitor for inducing a voltage in the receiver coil, wherein the receiver coil comprises two symmetrical segments with opposite orientation that are connected in series, wherein the transmitter coil surrounds the segments of the receiver coil or the transmitter coil is surrounded by the segments of the receiver coil.Type: GrantFiled: September 27, 2018Date of Patent: December 7, 2021Assignee: Renesas Electronics America Inc.Inventor: Erhard Müsch
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Patent number: 11195953Abstract: In a memory cell forming region including a dummy cell region, a plurality of fins which are parts of a semiconductor substrate, protrude from an upper surface of an element isolation portion and are formed adjacent to each other. A distance between a fin closest to a dummy fin among the plurality of fins and the dummy fin is shorter than a distance between two fins adjacent to each other. As a result, a position of an upper surface of the element isolation portion formed between two fins adjacent to each other and a position of an upper surface of the element isolation portion STI formed between the fin closest to the dummy fin and the dummy fin is lower than a position of an upper surface of the element isolation portion STI formed in a shunt region.Type: GrantFiled: September 16, 2019Date of Patent: December 7, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Katsuhiro Uchimura
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Patent number: 11186311Abstract: A control circuit connected to a control device configured to control a motor connected to a rotation shaft that is convertible into a turning angle of a turning wheel, the control circuit includes a main circuit configured to calculates a rotation number indicating a rotational state of the rotation shaft based on a detection signal from a rotation angle sensor configured to detect a rotation angle of the motor as a relative angle, a detection result communication unit configured to detect whether or not there is an abnormality in the main circuit and output a detection result to the control device, and a pseudo abnormality generating unit configured to set the detection result to be abnormal based on a pseudo abnormal signal from the control device.Type: GrantFiled: February 20, 2020Date of Patent: November 30, 2021Assignees: JTEKT CORPORATION, RENESAS ELECTRONICS CORPORATIONInventors: Masato Oda, Kenichi Kozuka, Hiromasa Suzuki, Masashi Oki
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Patent number: 11190805Abstract: Provided is a data processing device that reduces the amount of memory access in a case where data and an error control code are to be stored in a memory. The processing device includes a data compression section, a code generation section, a binding section, and a transfer section. The data compression section generates second data by performing a predetermined compression process on first data that is to be stored in a memory and of a predetermined data length. The code generation section generates an error control code for the first data or the second data. The binding section generates third data by binding the second data generated by the data compression section to the error control code generated by the code generation section. The transfer section transfers the third data generated by the binding section to the memory in units of the predetermined data length.Type: GrantFiled: March 30, 2020Date of Patent: November 30, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Katsushige Matsubara, Seiji Mochizuki, Keisuke Matsumoto
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Patent number: 11188373Abstract: A data processing device that can monitor properly the state of the interrupt processing of a virtual machine is provided. The data processing device according to an aspect of the present disclosure includes an arithmetic unit that executes multiple virtual machines, respectively, and an interrupt controller that instructs execution of the interrupt processing to the arithmetic unit with the virtual machine information to specify at least one of the multiple virtual machines. The interrupt controller includes a counter to count the number of interrupts for each virtual machine based on the virtual machine information.Type: GrantFiled: May 6, 2019Date of Patent: November 30, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yasuhiro Sugita
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Patent number: 11188488Abstract: Each master issues an access request including a read request and a write request to a memory. A cache caches the write request issued by the master. A central bus control system performs access control for the read request issued by each master and the write request output by the cache. A central bus control system performs access control for the write request issued by each master. The central bus control system performs access control in accordance with a free situation of a buffer of a memory controller. The central bus control system performs access control in accordance with a free situation of the cache.Type: GrantFiled: November 13, 2018Date of Patent: November 30, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Sho Yamanaka, Toshiyuki Hiraki, Nobuhiko Honda
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Patent number: 11182236Abstract: A method of determining a probabilistic metric for random hardware failure for an electronic system, such as a microcontroller, which comprises element and safety mechanisms (SMs) is disclosed. The safety mechanisms include first layer safety mechanisms (FL-SMs) and second layer safety mechanisms (SL-SMs). A first layer safety mechanism may provide at least partial coverage of failure of a part and a second layer safety mechanism may provide at least partial coverage of failure of a first layer safety mechanism. The method comprises calculating a first set of probabilities (KSM_i) associated with the first layer safety mechanisms, calculating a second set of probabilities (KDVF_n) associated with direct violation faults in the parts and calculating a third set of probabilities (KIVF_n) associated with indirect violation faults in the parts. The method includes obtaining the value of probabilistic metric for random hardware failure in dependence on the first, second and third sets of probabilities.Type: GrantFiled: April 13, 2017Date of Patent: November 23, 2021Assignee: Renesas Electronics CorporationInventors: Riccardo Vincelli, Agostino Cefalo
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Patent number: 11183589Abstract: To enhance the performance of a semiconductor device. Gate electrodes extending in a Y direction and applied with a gate potential, and emitter regions and base regions both applied with an emitter potential are formed in an active cell area. The plural emitter regions are formed so as to be separated from each other in the Y direction by the base regions. A plurality of hole discharge cell areas having a ring-shaped gate electrode applied with an emitter potential are formed within an inactive cell area. The hole discharge cell areas are arranged to be separated from each other along the Y direction. Thus, an input capacitance of an IGBT is reduced, and a switching loss at turn on of the IGBT is improved.Type: GrantFiled: April 27, 2020Date of Patent: November 23, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Nao Nagata
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Patent number: 11182128Abstract: A multiply-accumulate calculation device, a multiply-accumulate calculation method, and a system for efficiently performing a multiply-accumulate calculation are provided. The multiply-accumulate operation device includes a plurality of memory blocks that store a plurality of multiplied elements and performs a multiply-accumulate operation on input data. Each of memory blocks includes stores one bit value of the same bit digit of a plurality of multiplied elements. An input data generation unit generates input data by extracting data of a same bit digit from the plurality of multiplication elements. A control unit that accumulates and adds value of the multiply-accumulate operation result, and a data memory that stores the accumulated addition value as a multiplication element of the next multiply-accumulate operation.Type: GrantFiled: August 20, 2019Date of Patent: November 23, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Shunsuke Okumura
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Patent number: 11183510Abstract: After a dummy control gate electrode and a memory gate electrode are formed and an interlayer insulating film is formed so as to cover the gate electrodes, the interlayer insulating film is polished to expose the dummy control gate electrode and the memory gate electrode. Thereafter, the dummy control gate electrode is removed by etching, and then a control gate electrode is formed in a trench which is a region from which the dummy control gate electrode has been removed. The dummy control gate electrode is made of a non-doped or n type silicon film, and the memory gate electrode is made of a p type silicon film. In the process of removing the dummy control gate electrode, the dummy control gate electrode is removed by performing etching under the condition that the memory gate electrode is less likely to be etched compared with the dummy control gate electrode, in the state where the dummy control gate electrode and the memory gate electrode are exposed.Type: GrantFiled: December 4, 2017Date of Patent: November 23, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Tatsuyoshi Mihara
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Patent number: 11183471Abstract: A semiconductor device includes a semiconductor substrate, a multilayer wiring layer, a first inductor element, and a first capacitor element. The multilayer wiring layer is formed on the semiconductor substrate. The first inductor element and the first capacitor element are formed in the multilayer wiring layer. The first capacitor element is formed in the same layer as a layer in which the first inductor element is formed. The first capacitor element is formed inside the first inductor element in plan view.Type: GrantFiled: November 12, 2019Date of Patent: November 23, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Yasutaka Nakashiba
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Patent number: 11183569Abstract: A semiconductor device and a method of manufacturing a semiconductor device capable of suppressing breakdown due to current concentration while suppressing an increase in chip size are provided. According to one embodiment, a semiconductor device has a gate resistance on a main surface side of a semiconductor substrate, a first contact and a second contact connected to an upper surface of the gate resistance, and a carrier discharging portion that discharges the carrier formed in the semiconductor substrate below the gate resistance, the gate resistance having a first contacting portion to which a first contact is connected, a second contacting portion to which a second contact is connected, and a plurality of extending portions with one end connected to the first contacting portion and the other end connected to the second contacting portion. The gate resistance forms an opening between adjacent extending portions and the carrier discharge portion is formed in the opening.Type: GrantFiled: October 17, 2019Date of Patent: November 23, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Nao Nagata
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Patent number: 11178137Abstract: A data communication system has an IoT device, an information processing device capable of performing communication with the IoT device, and a server capable of performing communication with the IoT device and the information processing device. When a coupling request from the IoT device is received, the information processing device requests the server for a tentative common key which is temporarily valid. When a request for a tentative common key from the information processing device is received, the server generates a tentative common key and transmits the tentative common key to the information processing device. The information processing device transmits the received tentative common key to the IoT device, and the IoT device and the server perform authentication by using the tentative common key.Type: GrantFiled: May 10, 2019Date of Patent: November 16, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takahide Todoroki, Koichi Sato, Kazuhiko Noto
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Patent number: 11175189Abstract: An electronics device includes a power semiconductor device including a temperature detection diode, a first semiconductor integrated circuit device including a detection circuit for detecting VF from the temperature detection diode and a second semiconductor integrated circuit device. The second semiconductor integrated circuit device includes, an outside air temperature acquisition unit which acquires outside air temperature information, a storage which stores temperature characteristic data of the temperature detection diode and a first value based on a signal from the detection circuit at a first temperature and a temperature arithmetic processing unit which calculates a temperature of the power semiconductor device from a third value based on a signal from the detection circuit, the temperature characteristic data, the first temperature acquired by the outside air temperature acquisition unit and the first value.Type: GrantFiled: February 14, 2019Date of Patent: November 16, 2021Assignee: Renesas Electronics CorporationInventor: Makoto Tsurumaru
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Patent number: 11175321Abstract: Semiconductor device includes an element region in which the semiconductor element is provided, a semiconductor substrate including an outer peripheral region surrounding the element region, a plurality of semiconductor elements provided in an array-like in the element region. The element region includes a main circuit region in which the main circuit of semiconductor device is formed, and a sense circuit region in which a sense circuit for measuring the drain current flowing through the semiconductor element of the main circuit region is formed. Semiconductor element of the sense circuit region is surrounded by other semiconductor elements. Sense circuit region is covered with a main circuit source electrode which is connected to the semiconductor element of the main circuit region.Type: GrantFiled: July 8, 2020Date of Patent: November 16, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Takehiro Ueda
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Patent number: 11177395Abstract: A semiconductor device includes a semiconductor substrate SUB, a semiconductor layer EP formed on the semiconductor substrate SUB, a buried layer PBL formed between the semiconductor layer EP and the semiconductor substrate SUB, an isolation layer PiSO formed in the semiconductor layer EP so as to be in contact with the buried layer PBL, and a conductive film FG formed over the isolation layer PiSO via an insulating film IF, whereby a first capacitive element including the conductive film FG as an upper electrode, the insulating film IF as a capacitive insulating film, and the isolation layer PiSO as a lower electrode, is formed over the semiconductor substrate SUB.Type: GrantFiled: March 9, 2020Date of Patent: November 16, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Eisuke Kodama
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Patent number: 11177235Abstract: The semiconductor device includes a solder ball connected to a pad, and located below the pad, a first wiring electrically connected to the pad, and located above the pad, and a second wiring electrically connected to the first wiring. At this time, a width of the first wiring is greater than a width of the second wiring. Accordingly, high-frequency noise can be reduced while improving signal transmission characteristics.Type: GrantFiled: December 31, 2019Date of Patent: November 16, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Ryuichi Oikawa
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Patent number: 11176689Abstract: A first comparator compares first input data with second input data, and provides one when the first input data is larger than the second input data and zero when the first input data is equal to or smaller than the second input data as a first comparison result. A data generator generates data based on the second input data. A second comparator compares the first input data with the generated data, and provide one when the first input data is larger than the generated data and zero when the first input data is equal to or smaller than the generated data as a second comparison result. A data initializer initializes third input data. An adder adds the first and second comparison results to the third input data initialized in advance, and to provide the added data as the current third input data.Type: GrantFiled: December 7, 2017Date of Patent: November 16, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hanno Lieske
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Patent number: 11171086Abstract: A semiconductor device includes a base member, a multilayer wiring layer, and a first resistive element. The multilayer wiring layer is formed on the base member. The first resistive element is formed in the multilayer wiring layer. The first resistive element includes a first conductive part, a second conductive part and a third conductive part. The second conductive part is formed over the first conductive part. The third conductive part electrically connects the first conductive part and the second conductive part with each other. A length of the third conductive part in a first direction along a surface of the base member is greater than a length of the third conductive part in a second direction along the surface of the base member and perpendicular to the first direction.Type: GrantFiled: December 2, 2019Date of Patent: November 9, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shunji Kubo, Koichi Ando, Eiji Io, Hideyuki Tajima, Tetsuya Iida