Abstract: In the conventional wireless communication device, the message propagation path becomes complicated and the message arrival takes a long time. According to one embodiment, the wireless communication device includes an advertising communication control unit that performs broadcast communication with a plurality of unspecified other device, and a connection communication control unit that performs one-to-one communication with a preset specific other device, and performs transmission and reception of a message using a connection communication control unit with another device in a connection cluster that can communicate with the connection communication control unit, and performs transmission and reception of a message using an advertising communication control unit by a wireless communication device permitted in the connection cluster with another device outside the connection cluster.

Abstract: An object of the present invention is to provide a terminal authentication device that can suppress a troublesome operation to authenticate a terminal when the terminal is connected to a network. A reception unit receives a beacon signal broadcasted from a terminal. A position determination unit determines the position of the terminal using the received beacon signal. A connection control unit controls the terminal to be connected to a mesh network in the case where the determined position of the terminal is within a predetermined authentication possible region.

Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a second surface opposite to the first surface, and having a first recess portion formed on the first surface, a first cladding layer located in the first recess portion, and a first optical waveguide formed on the first cladding layer. The first optical waveguide overlaps with the first cladding layer in plan view.

Abstract: After a MISFET is formed on a substrate including a semiconductor substrate, an insulating layer and a semiconductor layer, an interlayer insulating film and a first insulating film are formed on the substrate. Also, after an opening is formed in each of the first insulating film and the interlayer insulating film, a second insulating film is formed at each of a bottom portion of the opening and a side surface of the opening and also formed on an upper surface of the first insulating film. Further, each of the second insulating film formed at the bottom portion of the opening and the second insulating film formed on the upper surface of the first insulating film is removed by etching. After that, an inside of the opening is etched under a condition that each of the first insulating film and the second insulating film is less etched than the insulating layer.

Abstract: A method of manufacturing a split-gate type nonvolatile memory improving reliability and manufacturing yield. In a method of manufacturing a split-gate type nonvolatile memory in which a memory gate electrode is formed prior to a control gate electrode, a protective film is formed to cover the gate insulating film exposed between control gate electrodes before unnecessary control gate electrodes are removed.

Abstract: A semiconductor device includes a first wiring having a first portion, a second portion, a third portion provided between the first portion and the second portion, memory cells connected to the third portion of the first wiring, a field effect transistor having a drain connected to the second portion, and a gate, and a second wiring provided in parallel with the first wiring. The third portion of the first wiring includes a fourth portion located nearest to the first portion and a fifth portion located nearest to the second portion. The first wiring further includes a sixth portion disposed between the first portion and the fourth portion. The memory cells include a first memory cell connected to the fourth portion and a second memory cell connected to the fifth portion. The second wiring is electrically connected between the sixth portion and the gate of the field effect transistor.

Abstract: A semiconductor device capable of executing a plurality of tasks in real time and improving performances is provided. The semiconductor device comprises a plurality of processors and a plurality of DMA controllers as master, a plurality of memory ways as slave, and a real-time schedule unit for controlling the plurality of masters such that the plurality of tasks are executed in real time. The real-time schedule unit RTSD uses the memory access monitor circuit and the data determination register to determine whether or not the input data of the task has been determined, and causes the task determined to have the input data determined to have been determined to be executed preferentially.

Abstract: A semiconductor device capable of suppressing a sharp change in current consumption and a self-diagnosis control method thereof are provided. According to one embodiment, the semiconductor device 1 includes a logic circuit, which is a circuit to be diagnosed, a self-diagnostic circuit for diagnosing the logic circuit, and a diagnostic control circuit for controlling the diagnosis of the logic circuit by the self-diagnostic circuit, and the diagnostic control circuit includes a diagnostic abort control circuit for gradually stopping the diagnosis of the logic circuit by the self-diagnostic circuit when the semiconductor device receives a stop signal instructing the stop of the diagnosis of the logic circuit by the self-diagnostic circuit.

Abstract: Exemplary embodiments may include a device with an input power component, a system supply component, an inductive charger component operatively coupled to the input component and the system component, and a direct charger component operatively coupled to the inductive charger and the system component. Exemplary embodiments may further include an input node of the inductive charger component and an input node of the direct charger component operatively coupled to an output node of the input power component at a first device node. Exemplary embodiments may also include a method of receiving an input power signal, obtaining a charging condition, entering a first charging state, in accordance with the obtained charging condition satisfying a first charging condition, and entering a second charging state, in accordance with the obtained charging condition satisfying a second charging condition.

Abstract: A search circuit includes a search table including a plurality of entry data, a search processing unit receiving a search key and performing a binary search operation for the search table. Each of the plurality of entry data includes a search data, a prefix length data and a search result data. The search processing unit reads one of the plurality of entry data from the search table according to a binary search operation, specifies a search target range based on the search data and the prefix length data in the read entry data, determines whether the search key is included in the search target range, and outputs the search result data of the read entry data based on a determination result.

Abstract: One or more embodiments are directed to a multiport power delivery architecture that reduces the cost and maximizes the power utilization. According to some aspects, an adapter power add-up feature of the embodiments can combine the power of two or more adapters. The total power can be used to support CPU Turbo events and Quick Charge function. In one aspect, one charger operates as voltage source or current source and the other(s) as current source(s). When the system demand is high enough for all chargers may operate as current sources, the battery will supply the rest of the system demand. The proposed implementation of adapter power add-up feature can enable simple control scheme. Customers can set up BGATE control priorities to determine which charger to handle the BGATE control.

Abstract: A position sensor is presented. Some embodiments of a position sensor according to some embodiments includes a position sensor that includes a transmission coil; receive coils, the receive coils including at least one polarity change; a target configured to transit across the receive coils; and a controller configured to drive the transmission coil, receive signals from the receive coils, and provide a position response indicative of the target position over the receive coils, wherein the position response exhibits a first linear region of a first slope and a second linear region of a second slope.

Abstract: One or more embodiments are directed to a multiport power delivery architecture that reduces the cost and maximize the power utilization. According to some aspects, embodiments solve problems associated with charging a battery with multiple adapter. Some embodiments enable supplying system load and charging a battery from two or more adapters simultaneously through a single sensing resistor.

Abstract: A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.

Abstract: The present invention provides a configuration capable of further suppressing power required for monitoring connection between devices. The device includes a controller capable of selecting an active state and a low power consumption state, and a switch device for controlling electrical connection/disconnection between an interrupt signal line and a bus in accordance with an output signal from the controller. In the low power consumption state, the controller returns to the active state when the potential appearing on the interrupt signal wiring substantially matches the potential of the bus, and after the return to the active state, provides the output signal to the switch device to electrically connect the interrupt signal wiring and the bus.

Abstract: The abnormal power supply voltage detection device has a function of accurately detecting the abnormal voltage in accordance with the characteristics of the semiconductor element for each semiconductor chip. Circuit group for operating the adjustment function has a function of preventing the influence of the power supply voltage of the logic system such as control in the semiconductor product malfunctions becomes abnormal. Furthermore, it has a function of detecting the abnormal voltage of the various power supplies in the semiconductor product. It also has a function to test the abnormal voltage detection function in the normal power supply voltage range during use of semiconductor products.

Abstract: To provide a correction method of resolver correction device and resolver correction device that can reduce rotation angle (the rotation speed) detection error caused by resolver. An excitation signal supply circuit supplies an excitation signal of an excitation frequency to the resolver during a normal operation, for supplying the excitation signals of a plurality of frequencies including the excitation frequency to the first phase shifter or the second phase shifter during a calibration operation. A shift amount searching circuit searches the first shift amount setting value for each frequency of the excitation signal such that the first shift amount becomes 45 degrees, and the second shift amount setting value for each frequency of the excitation signal such that the second shift amount becomes 135 degrees, while referring to the detection result of the phase difference detection circuit during the calibration operation, and stores in the correction table.

Abstract: One or more embodiments relate to a reference voltage control circuit for a buck-boost converter. According to certain aspects, embodiments can increase or decrease the reference voltage for an error amplifier for controlling a pulse width modulation (PWM) signal when there is a change in the mode of operation. In these and other embodiments, the reference voltage control circuit is configured to modify the reference voltage by increasing or decreasing the reference voltage when there is a change in the mode of operation, so as to reduce overshoot or undershoot disturbances in the regulated output voltage during such transitions.

Abstract: A semiconductor device includes a wiring substrate including a first surface, a second surface opposite to the first surface, a first heat dissipation conductive pattern formed on the first surface, a second heat dissipation conductive pattern formed on the first surface, a first wiring formed on the first surface, and a second wiring formed on the first surface. The semiconductor device also includes a semiconductor chip disposed on the wiring substrate and including a third surface and a fourth surface opposite to the third surface. In plan view, the second wiring is adjacent to the first and second heat dissipation conductive patterns without intervening any wiring and any conductive pattern between the second wiring and the first and second heat dissipation conductive patterns.

Abstract: A functional safety system with high reliability is provided. The functional safety system includes power source apparatuses VS1 and VS2, voltage monitoring apparatuses VM1 and VM2, semiconductor devices SC1 and SC2, interruption circuits IN1 and IN2, and a motor MT. A the voltage converting circuit DA1 of the voltage monitoring apparatus VM1 generates a detected voltage VA1 from a power source voltage VDD1 on the basis of a switching signal VC1, and a voltage converting circuit DA2 of the voltage monitoring apparatus VM1 generates a detected voltage VA2 from the power source voltage VDD1 on the basis of a switching signal VC1.