Abstract: A semiconductor system capable of reducing processing time in connection processing to a USB port is provided. The semiconductor system comprises TCPM and TCPC. The TCPM and the TCPC are communicably connected via the I2C bus. The TCPM has a connection detector. The TCPC in a CC logic and a controller. The CC logic embodies a state machine. The controller controls transitions in the state machine. The controller outputs a connected state transition notification when the connected state transitions to the connected state. The connection detector receives the connected state transition notification and detects the connection of the USB port. The TCPM performs a process corresponding to the connection detection by the connection detector.

Abstract: A semiconductor device includes a power MOS chip having a source electrode on a surface and a control chip mounted on a portion of the power MOS chip, wherein, viewing from a first outer edge of the power MOS chip extending in a first direction to the control chip, a first column bonding pad and a second column bonding pad are formed in a region of the source electrode where the control chip is not mounted, and wherein a distance between a second outer edge of the power MOS chip extending in a second direction and the first column bonding pad is longer than a distance between the second outer edge and the second column bonding pad.

Abstract: A first amorphous film including hafnium, oxygen and a first element is formed, and a plurality of grains including a second element which differs from any of hafnium, oxygen and the first element is formed on the first amorphous film. An insulating film including a third element that differs from any of hafnium and the second element is formed over the plurality of grains and the first amorphous film, thereby forming a plurality of grains including the second element and the third element. A second amorphous film including the same materials as those of the first amorphous film is formed on the plurality of grains and the first amorphous film. By performing heat treatment, the first amorphous film and the second amorphous film are crystallized to form a first ferroelectric film which is an orthorhombic and a second ferroelectric film which is an orthorhombic, respectively.

Abstract: A failure analysis apparatus is an apparatus for analyzing a failure of a semiconductor device including a memory circuit and includes a storage device and a processor. The storage device stores EDA data including size values of a memory cell in the memory circuit, size values of a peripheral circuit in the memory circuit and arrangement spacing values of the peripheral circuit, and layout data of the semiconductor device. The processor converts logical addresses and I/O value of a fail bit obtained by testing the memory circuit into physical addresses using predetermined arithmetic expressions, and converts the physical addresses into physical coordinate values using the size values of the memory cell, the size values of the peripheral circuit, and the arrangement spacing values of the peripheral circuit.

Abstract: To securely realize updating of a key shared between an apparatus on a transmission side and an apparatus on a reception side. A second apparatus encrypts a new shared key by an encryption processing unit, issues a signature for the encrypted new shared key from a signature processing unit, and transmits the signature and the encrypted new shared key to a first apparatus. When a signature processing unit fails in verifying the signature, the first apparatus performs control to prohibit at least one of processing executed after reception of the encrypted new shared key and required to store the new shared key into a storage unit.

Abstract: A method of manufacturing a semiconductor device includes: providing a substrate, forming a first opening, forming a first insulating layer, forming a second opening, embedding a conductive layer, forming a protective layer, and performing CMP. The substrate includes a semiconductor substrate and a semiconducting layer. The conductive layer is embedded in the second opening so that a gap along a thickness direction of the semiconducting layer is formed. The protective layer is formed in the second opening on at least a portion of a surfaces of the conductive layer. In the CMP step, a portion of the conductive layers formed outside the second opening is removed.

Abstract: The present invention solves a new problem that may occur when Try.SRC or Try.SNK is adopted. A controller is used to implement a DRP-compliant device that can be both power supply side and power reception side according to the USB Type-C standard. The controller is configured to be able to execute a first process of determining whether or not the Port Power Role of the opposing device is Try.SRC when the Power Role of the own device is determined to be Sink meaning the power receiver according to the sequence with the opposing device, which is the connected device, and a second process of switching the Port Power Role of the own device to SRC only and continuing the sequence with the opposing device if the Port Power Role of the opposing device is Try.SRC.

Abstract: A semiconductor device including a multilayer wiring layer comprising a first wiring, a first insulating film formed on the multilayer wiring layer and having a first opening exposing a portion of the first wiring, a second insulating film formed on the first insulating film and having a second opening continuing with the first opening, and an inductor formed of the first wiring, and a second wiring electrically connected with the first wiring through a via formed in the first opening. A side surface of the via contacts with the first insulating film, and does not contact with the second insulating film.

Abstract: A semiconductor device includes first and second terminals, a reference resister being coupled between the first and second terminals, third and fourth terminals, a sensor resister being coupled between the third and fourth terminals, a first buffer which supplies a first reference voltage to the first terminal, a second buffer which supplies a second reference voltage to the fourth terminal, a reference voltage generation circuit which supplies one of first and second voltages alternately in a time division manner as the first reference voltage and supplies the other as the second reference voltage, a first analog-to-digital conversion circuit which performs analog-to-digital conversion on a signal line coupled to the third terminal, an RC filter disposed on the signal line, a noise detector which detects noise of the signal line, wherein a time constant of the RC filter is changed based on a result of the noise detector.

Abstract: Example implementations includes a method of partitioning a non-transitory memory device by detecting a boot state of a processing device including a non-transitory memory device, identifying a startup state of the processing device based on the boot state, and partitioning the memory device into at least one secure address region, in accordance with a determination that the startup state satisfies an operating state condition. Example implementations also include a method of generating a secure partition associated with a non-transitory memory device by identifying a target processing instruction restricted to execution at a secure subsystem of a processing device, assigning to the target processing instruction a secure address, associating the secure address with a secure address region of a non-transitory memory device of the processing device, and generating a secure partition table including the secure address.

Abstract: An apparatus includes an amplifier circuit including a first transistor and a second transistor. The first transistor may include a gate having a gate oxide with a first thickness and a first gate length. The second transistor may include a gate having a gate oxide with a second thickness and a second gate length. The first transistor and the second transistor may be connected in a cascode configuration and the second thickness and the second gate length are greater than the first thickness and the first gate length, respectively.

Abstract: A semiconductor device includes a plurality of first wires formed in a first layer, a plurality of second wires formed to intersect the plurality of first wires in a second layer stacked on the first layer, a plurality of first vias formed at intersections of the plurality of first wires and the plurality of second wires, and an inductor formed in a third layer stacked on the first layer and the second layer.

Abstract: Fins lined up in a Y direction, a control gate electrode and a memory gate electrode each extending in the Y direction so as to straddle the fins, a plurality of first plugs electrically connected with a drain region formed in each of the fins, and a plurality of second plugs electrically connected with a source region formed in each of the fins are formed. Here, a N-th plug of the plurality of first plugs lined up in the Y direction is coupled with each of (2N?1)-th and 2N-th fins in the Y direction. Also, a N-th plug of the plurality of second plugs lined up in the Y direction is coupled with each of 2N-th and (2N+1)-th fins in the Y direction.

Abstract: A program is executed in an information processing device including a processor and a memory. The program allows the processor to execute a step of, on the basis of a simulation result of a model in the case where a series of blocks having an input block, one or more operation blocks, and an output block are allowed to operate at a predetermined clock frequency, deciding a new clock frequency of a target block that is allowed to operate at a clock frequency lower than the predetermined clock frequency, and a step of setting the conversion ratios of conversion blocks so as to execute a simulation of the model in which the target block is allowed to operate at the new clock frequency lower than the predetermined clock frequency and the remaining blocks are allowed to operate at the predetermined clock frequency.

Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.

Abstract: A method and apparatus for microcontroller (MCU) memory relocation. The MCU includes a central processing unit (CPU) and memory, but lacks a memory management unit (MMU). In one embodiment of the method, a first program is selected for execution by the CPU. The first program is one of a plurality of programs stored in the memory of the MCU. Each of the programs includes position dependent instructions. The programs are compiled from source code written in position dependent code.

Abstract: A semiconductor device capable of suppressing propagation of a crack caused by a temperature cycle at a bonding part between a bonding pad and a bonding wire is provided. A semiconductor device according to an embodiment includes a semiconductor chip having bonding pads and bonding wires. The bonding pad includes a barrier layer and a bonding layer formed on the barrier layer and formed of a material containing aluminum. The bonding wire is bonded to the bonding pad and formed of a material containing copper. An intermetallic compound layer formed of an intermetallic compound containing copper and aluminum is formed so as to reach the barrier layer from the bonding wire in at least a part of the bonding part between the bonding pad and the bonding wire.

Abstract: A USB test device for testing a power feed device having a USB plug includes: a connector connected to the USB plug; a communication control unit that communicates with the power feed device through a communication line of the connector; a load control unit capable of controlling a load of a power supply line of the connector receiving power supply from the power feed device; a test control unit that gives an instruction to the load control unit based on power supply information which was obtained by the communication control unit and which is about a combination of electric power that can be supplied from the power feed device, and examines a state of power supply to the load from the power feed device; and a display unit that displays a result of examination by the test control unit.

Abstract: The invention relates to an arrangement and a method performing data exchange between various integrated circuits, IC, (3,4,5,6,7) in an automotive control system wherein the data are exchanged by a bus and has the object to enable ASIL C/D system coverage and to tie various ICs (clocks, regulators, memory interfaces, sensor signal conditioners, power management ICs etc.) This is solved the data are exchanged by a bus being ASIL C/D compliant and forming a common protocol to exchange information among the integrated circuits (3,4,5,6,7). The method is solved by functions implemented within the bus as setting the frequency of operation; arbitrating roles of the integrated circuits as master or slave device; checking integrity of exchanged data; frame repetition; detecting bus stuck-at failure modes; filtering or denouncing failures and warnings from peripheral devices; detecting remote out of specification local clock; and monitoring and predicting system reliability and profiling maintenance events.

Abstract: A quadrature phase clock generator includes a tunable polyphase filter and a phase detector. The tunable polyphase filter is configured to receive an input clock signal and generate four quadrature phase clock signals. The phase detector is coupled to receive at least two of the four quadrature phase clock signals and generate a control signal adapted to tune the polyphase filter based on the received quadrature phase clock signals. Further, the phase detector is configured to provide the control signal to the polyphase filter in a feedback loop. Based on the control signal from the phase detector, the tunable polyphase filter generates four tuned quadrature phase clock signals as output phase clock signals.