Patents Assigned to RENESAS
  • Patent number: 11217599
    Abstract: A plurality of select transistors are formed in a first region of a semiconductor substrate, a plurality of memory transistors are formed in a second region of the semiconductor substrate, and a drain region of the select transistor and a source region of the memory transistor are electrically connected to form a memory cell. Here, the first region and the second region are arranged with each other in a gate width direction of the select transistor and the memory transistor.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 4, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideaki Yamakoshi
  • Patent number: 11215564
    Abstract: The visual inspection device comprises a first illumination device capable of illuminating an top surface of an inspection object, a second illumination device capable of illuminating a bottom surface opposite to the top surface of the inspection object and a first imaging device capable of capturing the top surface of the inspection object. A relative position of each of the first illumination device and the second illumination device and the inspection object are adjusted such that a part of the captured image captured by the first imaging device is disappeared.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: January 4, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideki Wada
  • Patent number: 11217989
    Abstract: A drive device comprises a sensor for detecting a state of stress applied to a power transistor, a threshold voltage setting circuit for outputting a threshold voltage, an anomaly monitor circuit for determining whether or not a state of stress is abnormal by comparing a detected voltage of the sensor with the threshold voltage, and a control circuit for fixing the power transistor to either on or off when the state of stress is determined to be abnormal by the anomaly monitor circuit. When an operating mode is a test mode, the control circuit tests whether the anomaly monitor circuit determines the state of the stress is abnormal or not by switching a level of the threshold voltage set by the threshold voltage setting circuit so as to determine that a state of the stress applied to the power transistor is abnormal in the normally operating anomaly monitor circuit.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: January 4, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shunichi Kaeriyama
  • Patent number: 11217605
    Abstract: The first gate insulating film is an insulating film made of silicon oxide, and to which hafnium (Hf) is added without addition of aluminum (Al). Also, the second gate insulating film is an insulating film made of silicon oxide, and to which aluminum is added without addition of hafnium. The third gate insulating film is an insulating film made of silicon oxide, and to which aluminum is added. Further, the fourth gate insulating film is an insulating film made of silicon oxide, and to which hafnium is added. Accordingly, it is possible to reduce the power consumption of the semiconductor device.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: January 4, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shibun Tsuda
  • Patent number: 11214297
    Abstract: A motor control system includes a first MCU and a second MCU. The first MCU includes an error detection unit, a resolver digital converter, and a first PWM generation unit. The resolver digital converter includes an encoder unit, which generates encoder pulses based on angle information and outputs the encoder pulses to the second MCU. The error detection unit outputs an error signal to the second MCU, when an error is detected in the first MCU. The first MCU controls the resolver digital converter to operate using a backup clock supplied from the second MCU.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: January 4, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuro Nishikawa, Takao Koike, Shinya Abe
  • Patent number: 11217682
    Abstract: Provided is a stable manufacturing method for a semiconductor device. In the manufacturing method for a semiconductor device, first, fins with an equal width are formed in each of a memory cell portion and a logic portion of a semiconductor substrate. Then, the fins in the logic portion are etched with the fins in the memory cell covered with a mask film, thereby fabricating fins in the logic portion, each of which is narrower than the fin formed in the memory cell portion.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: January 4, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masaaki Shinohara
  • Patent number: 11212435
    Abstract: A semiconductor device includes a distortion correction unit that performs correct distortion processing on a captured image, a SRAM that stores image data after the distortion correction processing, a filter processing unit that receives the image data after the distortion correction processing from the SRAM and that performs smoothing filter processing on the image data after the distortion correction processing, after the image data after the distortion correction processing having a size required for the smoothing filter processing is stored in the SRAM, and an image reduction unit that performs reduction processing on image data after the smoothing filter processing.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: December 28, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Akihiro Yamamoto
  • Patent number: 11210530
    Abstract: A semiconductor device for an apparatus having a movement drive unit and an image unit, includes an image detection unit, an image recognition unit and control unit. The image detection unit detects an object in a captured image and cuts out an image area including the object from the captured image as an object detection area image. The image recognition unit performs an image recognition processing for the object detection image area and output a recognition probability of the object. The control unit controls at least one of a moving speed of the movement drive unit and an imaging interval of the image unit based on the recognition probability.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: December 28, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Remi Miyamoto, Keisuke Matsumoto
  • Patent number: 11211349
    Abstract: A semiconductor device comprising: bonding pads formed in the first wiring layer; and first wirings and a second wiring formed in a second wiring layer provided one layer below the first wiring layer. Here, a power supply potential and a reference potential are to be supplied to each first wiring and the second wiring, respectively. Also, in transparent plan view, each of the first wirings is arranged next to each other, and is arranged at a first position of the second wiring layer, that is overlapped with the bonding region of the first bonding pad. Also, in transparent plan view, the second wiring is arranged at a second position of the second wiring layer, that is overlapped with a first region located between the first bonding pad and the second bonding pad. Further, a width of each first wiring is less than a width of the second wiring.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: December 28, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Seiya Isozaki, Tatsuya Kobayashi, Kota Jinno
  • Patent number: 11208067
    Abstract: An ECU includes a boosting circuit that boosts an input power supply voltage, a backup capacitor that charges a backup power supply in accordance with a boosted voltage boosted by the boosting circuit, an airbag ignition circuit that drives an airbag with the backup power supply charged by the backup capacitor as a driving power supply, and a bidirectional current limiting unit that limits a charging current flowing from the boosting circuit to the backup capacitor and limits a backflow current flowing from the backup capacitor to the boosting circuit.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: December 28, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yutaka Hayashi
  • Patent number: 11211406
    Abstract: To provide a semiconductor device having a thin-film BOX-SOI structure and capable of realizing a high-speed operation of a logic circuit and a stable operation of a memory circuit. A semiconductor device according to the present invention includes a semiconductor support substrate, an insulation layer having a thickness of at mast 10 nm, and a semiconductor layer. In an upper surface of the semiconductor layer, a first field-effect transistor including a first gate electrode and constituting a logic circuit is formed. Further, in the upper surface of the semiconductor layer, a second field-effect transistor including a second gate electrode and constituting a memory circuit is formed. At least three well regions having different conductivity types are formed in the semiconductor support substrate.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: December 28, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryuta Tsuchiya, Toshiaki Iwamatsu
  • Publication number: 20210399704
    Abstract: The invention relates to a variable gain system, particularly for optical receiver systems, having: an input for an electronic signal, at least two variable gain amplifiers, and an output for an amplified electrical signal, wherein the at least two variable gain amplifiers are connected in parallel to the input and the output aggregates the signals of the at least two variable gain amplifiers.
    Type: Application
    Filed: June 14, 2021
    Publication date: December 23, 2021
    Applicant: Renesas Electronics America Inc.
    Inventor: Philippe CONVERS
  • Patent number: 11204799
    Abstract: A semiconductor device capable of suppressing performance degradation and systems using the same are provided. The semiconductor device includes a plurality of processors CPU1 and CPU2, a scheduling device 10 (ID1) connected to the processors CPU1 and CPU2 for controlling the processors CPU1 and CPU2 to execute a plurality of tasks in real time, memories 17 and 18 accessed by the processors CPU1 and CPU2 to store data by executing the tasks, and access monitor circuits 15 for monitoring accesses to the memories by the processors CPU1 and CPU2. When an access to the memory is detected by the access monitor circuit 15, the data stored in the memory 18 is transferred based on the destination information of the data stored in the memory 18.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: December 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuo Sasaki
  • Patent number: 11205655
    Abstract: A method for manufacturing a semiconductor device includes a step of reducing a thickness of a silicon oxide film embedded in an element isolation trench including fins in order to form protruded fins. In the step, the silicon oxide film is etched while covering part of an upper surface of the silicon oxide film with a resist pattern. At this time, the resist pattern is formed such that a distance between the fin and the resist pattern is equal to or less than a predetermined interval which is an arrangement interval of the plurality of fins.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 21, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tomohiro Hayashi
  • Patent number: 11205915
    Abstract: According to certain aspects, the present embodiments are related to systems and methods providing an autonomous adapter pass through mode in a battery charger. For example, when an adapter is connected to the battery charger, but the system is idling, embodiments allow for power from the adapter to be directly coupled to the battery charger output, and main switching to be stopped, thereby dramatically reducing battery charger current consumption. These and other embodiments provide various circuitry and techniques to ensure that the battery is protected in this mode. According to further aspects, the present embodiments provide for the charger itself to autonomously enter and exit the adapter pass through mode, thereby eliminating the need for excessive processing overhead in components external to the battery charger.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: December 21, 2021
    Assignee: Renesas Electronics America
    Inventors: John H. Carpenter, Jr., Mehul Shah, Michael Jason Houston
  • Patent number: 11201465
    Abstract: A semiconductor device including a digital circuit, a first ground potential line provided corresponding to the digital circuit, an analog circuit, a second ground potential line respectively provided corresponding to the analog circuit, and a bidirectional diode group provided between the first ground potential line and the second ground potential line.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 14, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuyuki Morishita
  • Patent number: 11199620
    Abstract: A radar device is provided which is capable of highly accurate distance calculation by a simple method. The radar device includes: a transmission circuit which transmits radio waves; an adjustment circuit which adjusts transmission angles of the radio waves transmitted from the transmission circuit; a reception circuit which receives plural signals which are the radio waves transmitted, based on adjustment made by the adjustment circuit, from the transmission circuit and respectively reflected from an object; and a signal processing circuit which, by processing the received signals, calculates a distance to the object. The signal processing circuit includes a buffer which stores signal strength data on the signals received by the reception circuit, the received signals respectively corresponding to the transmission angles, and a correction circuit which performs correction processing on equidistance-based portions of the signal strength data on the received signals stored in the buffer.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: December 14, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuji Motoda
  • Patent number: 11194380
    Abstract: It is an object of the present invention to provide a technique capable of reducing power consumption of a semiconductor device even when the semiconductor device operates at high speed. The semiconductor device includes a module for outputting a signal, a delay element, a first output circuit having an input and an output, a first external terminal connected to the output of the first output circuit and to be connected to a signal wiring, and a second external terminal. The input of the first output circuit receives the signal delayed by the delay element. The second external terminal receives the signal without passing through the delay element. The signal of the second external terminal is used to change the potential level of the signal wiring to be connected to the first external terminal before the first output circuit changes the potential of the first external terminal based on the delayed signal.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: December 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naotaka Kawakami, Toshiro Fujisaki
  • Patent number: 11193974
    Abstract: A failure diagnostic apparatus includes a path calculation unit which calculates, for each input pattern to a diagnosis target cell, a path affecting an output value of the diagnosis target cell when a failure is assumed as an activation path, a path classification unit which classifies the activation path associated with the input pattern for which the diagnosis target cell has passed a test and the activation path associated with the input pattern for which the diagnosis target cell has failed the test, a path narrowing unit which calculates a first failure candidate path, a second failure candidate path and a normal path of the diagnosis target cell based on classified activation paths, and a result output unit which outputs information on the first failure candidate path, the second failure candidate path and the normal path.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: December 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukihisa Funatsu, Kazuki Shigeta
  • Patent number: 11195782
    Abstract: Reliability of a semiconductor device is improved. In the semiconductor device SA1, a snubber capacitor pad SNP electrically connected to the capacitor electrode of the snubber capacitor is formed on the surface of the semiconductor chip CHP.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: December 7, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoki Fujita, Hiroyuki Nakamura