Abstract: By changing the characteristic impedance of the transmission line depending on the location, the transmission line functions as a band-pass filter.

Abstract: Cross talk among wirings formed in an interposer is reduced while increase in a parasitic capacitance among the wirings formed in the interposer is suppressed. A semiconductor device has an interposer including a first wiring layer, a second wiring layer formed above the first wiring layer, and a third wiring layer formed above the second wiring layer. In a plan view, a first signal wiring formed in the first wiring layer and a reference wiring formed in the second wiring layer are distant from each other. Similarly, in a plan view, the reference wiring formed in the second wiring layer and a third signal wiring formed in a third wiring layer are distant from each other.

Abstract: Systems and methods for determining a likelihood of an occurrence of an anomaly in a sensor are described. A processor can receive a first measurement of a first capacitance change between a first port and a second port of a device connected to the sensor. The first measurement can be obtained in response to the first port being configured to perform a first function, and in response to the second port being configured to perform a second function. The processor can receive a second measurement of a second capacitance change between the first and second ports. The second measurement can be obtained in response to the first port being configured to perform the second function, and in response to the second port being configured to perform the first function. The processor can determine the likelihood of the occurrence of the anomaly based on the first and second measurements.

Abstract: A semiconductor device includes a first terminal receiving a first signal, a second terminal receiving a second signal, a noise extraction analysis unit extracting a signal of a specific frequency component from the first and the second signal, a feedback unit generating a feedback signal based on a magnitude of the signal of the specific frequency component to cancel the signal of the specific frequency component superimposed on the first and the second signal, and third terminal outputting to the feedback signal to outside.

Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.

Abstract: A semiconductor device includes an analog-digital conversion circuit that converts a voltage at a node between a reference resistor and a sensor resistor into output data, the reference resistor and the sensor resistor being connected in series. The semiconductor device calculates a resistance value of the sensor resistor using a first output data obtained in a first conversion phase and second output data obtained in a second conversion phase. In the first conversion phase, a high potential side voltage is applied to one end of the reference resistor and a low potential side voltage is applied to one end of the sensor resistor. In the second conversion phase, the low potential side voltage is applied to one end of the reference resistor and the high potential side voltage is applied to one end of the sensor resistor.

Abstract: The electronic device includes first and second semiconductor components. And, the electronic device includes a sealing body for sealing the first semiconductor component (i.e., the logic chip). A plurality of through conductors electrically connected to the first semiconductor component and/or the second semiconductor component is formed in the sealing body. In plan view, the sealing body has a first region in which the first semiconductor component is located, a second region located on a periphery of a first surface of the sealing body, a third region located between the second region and the first region, and a fourth region located between the second region and the third region. The plurality of through conductors is arranged most in the second region. The number of the plurality of through conductors located in the third region is larger than the number of the plurality of through conductors located in the fourth region.

Abstract: A semiconductor device includes first and second power supply terminals to which a first power supply voltage is supplied, a third power supply terminal to which a second power supply voltage is supplied, a power supply wiring coupled to the first and second power supply terminals, an abnormality detection circuit which diagnoses the first power supply terminal, a first current generation circuit which flows a current from the power supply wiring to the third power supply terminal in a diagnosis, and a second current generation circuit which couples to the power supply wiring at a vicinity of the first power supply terminal and flows a current from the power supply wiring to the third power supply terminal in the diagnosis. And, the abnormality detection circuit compares a voltage of the first current generation circuit with a voltage of the second current generation circuit in the diagnosis.

Abstract: A phase-locked loop (PLL) performs hitless switching from a first reference clock (ref1) to a second reference clock (ref2) by entering holdover mode (418), and aligning the feedback clock (fbclk) to the second reference clock while in holdover mode. The alignment is performed by adjusting a divisor input (D) for the multi-mode divider (128) that divides the output clock frequency (PLLout) to generate the feedback clock. Other features are also provided.

Abstract: A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.

Abstract: A semiconductor device with an insulated-gate field-effect transistor and its manufacturing method. The cell region EFR defined in the first region of one main surface side of semiconductor substrate (SUB), an insulated gate-type field-effect transistor (MFET) is formed, the gate pad region GPR defined in the first region, snubber circuit SNC is formed snubber region SNR is defined. Within the first and second regions, first and second deep trenches spaced apart from each other are formed, and at least one width of the plurality of second deep trenches formed in the second region is smaller than that of the first deep trench formed in the first region.

Abstract: Increase the effective data rate of high-speed data communication. It has a memory unit, a reception signal line, and a transmission signal line capable of communicating with an external device via a control circuit and an equalizer, controllers for controlling transmission and reception of signals to and from the external device, and a correction coefficient associated with an identification information and the identification information of the external device. The control circuit sets the correction coefficient associated with the identification information to the equalizer.

Abstract: A semiconductor device includes a first semiconductor chip on which a first circuit is formed and a second semiconductor chip on which two circuits are formed. In the first semiconductor chip, a first inductor on the transmitting side electrically connected with the first circuit and a second inductor on the receiving side electrically connected with the second circuit via the bonding wire are formed. In plan view, the first inductor and the second inductor are disposed so as not to overlap each other, and are arranged along each other.

Abstract: The power line communication device detects inverter noise from the voltage waveforms of the power line, and executes the output of the transmission signal in a period in which it is determined that the signal amplitude of the transmission signal in the transmission processing unit exceeds a predetermined value from the output amplitude of the inverter noise, and stops the output of the transmission signal in other periods.

Abstract: In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.

Abstract: A controller for providing a DRP port according to USB Type-C standard. A state manager coupled to a power manager for controlling charging and discharging of a battery. A signal transmission module for exchanging a signal with a connection destination via a communication line in the USB cable according to an instruction from the state manager. The signal transmission module is possible to indicate the communication line whether the port is featured as the power supply side or the power reception side. When the port is featured as the power supply side, the state manager supplies an electric power stored in the battery to the connection destination and if the battery becomes the condition of Low Battery, the state manager stops supplying the electric power to the connection destination while maintaining the state that the port is featured as the power supply side.

Abstract: A semiconductor device includes an image acquisition circuit which acquires a plurality of captured image data obtained by capturing a plurality of images, an estimation source image generation circuit which cancels effects of initial color adjustment processing on each captured image data to generate image data of a plurality of estimation source images, a readjustment circuit which divides each estimation source image into a plurality of processing regions to perform color balance readjustment processing for each processing region, and an image synthesis circuit which synthesizes the image data of the plurality of estimation source images so that overlapping regions included in the estimation source images overlap each other to generate image data of a synthesized image.

Abstract: The semiconductor module includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes an optical device such as an optical waveguide and wiring formed over the optical device. The second semiconductor chip include semiconductor elements such as MISFET, and wiring formed over the semiconductor elements. A top surface of the first semiconductor chip is laminated with a top surface of the second semiconductor chip such that the first and second wirings are directly contacted with each other.

Abstract: A semiconductor module includes a semiconductor chip including wiring formed over a semiconductor element such as a MISFET, a sealing resin part MR covering the semiconductor chip such that the wiring is exposed, and an inductor formed in redistribution wiring. The inductor overlaps with the sealing resin part covering at least a side surface of the semiconductor chip in plan view.

Abstract: A master issues the valid data is specified when the data update processing is interrupted. The control unit 3 stores in the storage unit 2 the second update status flag 8_2, which indicates the update status of the first update status flag 8_1 and the second data 6_2, which indicate the update status of the first data 6_1, and the third update status flag 8_3, which indicates the update status of the valid indication flag 7. When the determination based on the valid instruction flag 7 is impossible, the usage data determination unit 4 determines which of the first data 6_1 and the second data 6_2 is valid based on the values of the first update status flag 8_1, the second update status flag 8_2, and the third update status flag 8_3.