Abstract: According to certain general aspects, the present embodiments relate generally to securing communication between ECUs. Example implementations can include a method of securely transmitting Controller Area Network (CAN) protocol frames via a CAN controller.

Abstract: A semiconductor device including a field-effect transistor having source and drain source regions, first and second gate electrodes and a protective diode connected to the transistor. The first gate electrode is formed over a first gate insulating film in a lower part of a trench. The second gate electrode is formed over a second gate insulating film in an upper part of the trench. The first gate electrode includes a first polysilicon film, and the second gate electrode includes a second polysilicon film, wherein an impurity concentration of the first polysilicon film is lower than an impurity concentration of the second polysilicon film.

Abstract: The semiconductor device includes a semiconductor chip including a first nonvolatile memory including a first memory block and a second memory block, CPU controlling the first nonvolatile memory, a first switch electrically connected to the first memory block and controlling the supply of the first power supply voltage to the first memory block, a second switch electrically connected to the second memory block and controlling the supply of the first power supply voltage to the second memory block, and a second nonvolatile memory electrically connected to each of the first switch and the second switch and storing flag information for controlling the first switch and the second switch, wherein the control of each of the first switch and the second switch is performed based on flag information indicating whether program data executed by CPU is written in the first memory block and the second memory block.

Abstract: An apparatus includes a plurality of monitoring circuits and a reset circuit. The monitoring circuits may each be configured to determine a status of one of a plurality of input signals, transmit one of the input signals to a PLL circuit and generate a loss signal in response to the status. The reset circuit may be configured to receive the loss signal and generate a reset signal in response to the loss signal. One of the input signals may be a primary input used by the PLL circuit. One of the input signals may be a secondary input that has been selected to replace the primary input. The reset signal may be configured to reset a feedback clock divider of the PLL circuit.

Abstract: Example implementations include a charging device with a capacitor divider circuit including a plurality of battery state inputs operably coupleable to a plurality of battery devices, and a pulse width modulation (PWM) generator operable to selectively charge the battery devices, a plurality of switching transistors each operatively coupled at a gate terminal thereof to a respective PWM control output of a plurality of PWM control outputs, and a flying capacitor operatively coupled at a first terminal thereof to a first plurality of the switching transistors, operatively coupled at a second terminal thereof to a second plurality of the switching transistors.

Abstract: A data transmitter is disclosed. The data transmitter includes a digest generator configured in response to receiving a set of data from a data source to generate a digest from the set of data using a cryptographic primitive. The data transmitter further includes a packet generator configured to generate a series of one or more packets carrying the set of data for transmission, wherein each packet in the series includes a header, the set of data, a footer and the digest.

Abstract: The semiconductor device includes a fin FA selectively protruded from an upper surface of a semiconductor substrate SB, a gate insulating film GF1 formed on an upper surface and a side surface of the fin FA and having an insulating film X1 and a charge storage layer CSL, and a memory gate electrode MG formed on the gate insulating film GF1. Here, the thickness of the charge storage layer CSL on the upper surface of the fin FA is larger than the thickness of the charge storage layer CSL on the side surface of the fin FA.

Abstract: Even under various conditions, stay of request on a bus is eliminated, and memory efficiency can be improved. Each of a master A, a master B, and a master X issues an access request to a memory. A memory controller receives an access request through a bus. A central bus control unit controls output of an access request issued by a master to the memory controller through granting the master an access right to the memory. The central bus control unit manages the number of rights that can be granted, which indicates the number of the access rights that can be granted, based on an access size of an access request issued by the master to which the access right is granted, and performs grant of the access right within a range of the number of rights that can be granted.

Abstract: A video encoding device includes a local decode generation unit for generating a reference image based on a result of encoding of a divided image, a compression unit for compressing the reference image to generate a compressed data, a reference image storage determination unit for determining whether to store the compressed data in a memory, and an inter-prediction unit for performing motion vector search for inter-coding based on a reference image stored in the memory. The reference image storage determination unit sets an allowable data amount used for storing the reference image for each determined area of the moving image data, and determines whether or not to store the compressed data obtained by compressing the reference image in the memory based on the allowable data amount. Inter-prediction unit sets the reference image corresponding to the compressed data stored in the memory as the search range of motion vector search.

Abstract: The lower surface of the wiring substrate includes a first region overlapping with the semiconductor chip mounted on the upper surface, and a second region surrounding the first region and not overlapping with the semiconductor chip. The first region includes a third region in which the plurality of external terminals is not arranged, and a fourth region surrounding the third region in which the plurality of external terminals is arranged. The plurality of external terminals includes a plurality of terminals arranged in the fourth region of the first region and a plurality of terminals arranged in the second region. The plurality of terminals includes a plurality of power supply terminals for supplying a power supply potential to the core circuit of the semiconductor chip, and a plurality of reference terminals for supplying a reference potential to the core circuit of the semiconductor chip.

Abstract: An integrated circuit, for example, a system-on-a-chip is disclosed. The integrated circuit includes a timing synchronisation unit including a hardware timer, for example, a gPTP timer. The integrated circuit also includes a non-Ethernet network interface, for example, a PCIe interface, for communicating with another integrated circuit having another hardware timer. The timing synchronisation unit is configured, in response to receiving a timing trigger from the other integrated circuit, to capture a local time t2. The timing synchronisation unit is further configured to provide the local time t2 to a processor for the processor to compute a timing offset between a remote time t1 of the other hardware timer which generated the timing trigger and the local time for time synchronisation.

Abstract: A memory cell, which is a nonvolatile memory cell, includes a gate dielectric film having charge storage layer capable of holding charges, and a memory gate electrode formed on the gate dielectric film. The charge storage layer includes an insulating film containing hafnium, silicon, and oxygen, an insertion layer formed on the insulating film and containing aluminum, and an insulating film formed on the insertion layer and containing hafnium, silicon, and oxygen.

Abstract: A simple battery and battery charger. In one embodiment, the battery charger includes an output terminal that provides a charging voltage Vout and charging current Iout. The battery is contained in a battery pack having an input terminal, which can be connected to the output terminal in order to receive Vout and Iout. The battery charger may include a first circuit for controlling the magnitude of Vout. The battery pack may include a second circuit that generates a control signal when the output terminal is connected to the input terminal. The first circuit is configured to control the magnitude of Vout based on the control signal.

Abstract: A semiconductor device includes an image data acquisition circuit which acquires a plurality of first captured image data and a plurality of second captured image data at a first time and a second time, an adjustment region determination circuit which detects a target object from the plurality of first captured image data, and determines an adjustment region by estimating a position of the target object at the second time, a color adjustment circuit configured to determine a color adjustment gain based on the adjustment region, and perform color balance adjustment processing on the plurality of second captured image data based on the color adjustment gain, and an image synthesis circuit configured to synthesize the plurality of second captured image data so that overlapping regions included in a plurality of images of the plurality of second captured image data overlap each other.

Abstract: A current source having an operational amplifier with positive input, negative input, negative output and positive output, negative input voltage connected to the positive input via a negative input resistor, positive input voltage connected to the negative input via a positive input resistor, the negative output is connected to the positive input via a first negative feedback resistor and to the negative input via a series connection of a first current sense resistor and a first positive feedback resistor, the positive output is connected to the negative input via a second negative feedback resistor and to the positive input via a series connection of a second current sense resistor and a second positive feedback resistor, a negative load output is between the first current sense resistor and the first positive feedback resistor, and a positive load output is between the second current sense resistor and the second positive feedback resistor.

Abstract: A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion.

Abstract: A semiconductor device capable of reducing power consumption is provided. A semiconductor device having a processor executing a plurality of tasks while switching the tasks in synchronization with a supplied operational clock signal includes: a processor-use-rate measuring unit configured to measure a use rate of the processor during a first term; and a frequency-dividing-value selecting circuit and a frequency dividing circuit configured to change a frequency of the operational clock signal supplied to the processor during a second term later than the first term on the basis of the use rate measured by the processor-use-rate measuring unit.

Abstract: A drive apparatus for a motor having a stator and a rotor, the drive apparatus including a current detection unit configured to detect, when the motor is rotating, each of multi-phase currents flowing through coils of the stator, and a control unit for controlling the motor by sensor-less control configured to convert the detected multi-phase currents into a d-axis current Id and a q-axis current Iq in a d-q coordinate system, calculate a phase error between an actual rotational position of the rotor and an imaginary rotational position thereof by comparing the d-axis current Id with a d-axis current command value Idref and comparing the q-axis current Iq with the d-axis current command value Idref, perform control so that the phase error gets closer to zero, and output voltage command values to a motor drive circuit.

Abstract: The power consumption of a circuit block outside a microcomputer and inside the same system is reduced. An electric power control system includes a first power supply circuit, a semiconductor device having a first circuit block operated by electric power supplied from the first power supply circuit, a state holding circuit that holds an operation state in the first circuit block according to the electric power, an electric power control circuit that controls the electric power supplied to the first circuit block according to the operation state, and a first terminal that outputs a first state signal corresponding to the operation state, a second power supply circuit that controls the supply of electric power according to the first state signal, and a second circuit block operated by the electric power supplied from the second power supply circuit.

Abstract: Example implementations include a method of generating a ramp down compensation voltage based at least partially on the a current sense voltage and an inductor voltage of an inductor at an inductor node, applying the ramp down compensation voltage to the inductor node, and in accordance with a first determination that the valley current sense voltage and the inductor voltage are not equal, modifying a predetermined capacitance of a system capacitor operatively coupled to the inductor node to a first modified capacitance.