Abstract: A semiconductor device includes a rectifier circuit that rectifies an AC input voltage, a zero-cross detection circuit that detects a zero-cross of the AC input voltage, a control circuit that turns on the rectifier circuit at a timing determined by the zero-cross detected by the zero-cross detection circuit and a predetermined phase angle, and the phase angle is set so that an output voltage of the rectifier circuit is gradually increased.

Abstract: The performances of a semiconductor device of a memory element are improved. Over a semiconductor substrate, a gate electrode for memory element is formed via overall insulation film of gate insulation film for memory element. The overall insulation film has first insulation film, second insulation film over first insulation film, third insulation film over second insulation film, fourth insulation film over third insulation film, and fifth insulation film over fourth insulation film. The second insulation film is an insulation film having charge accumulation function. Each band gap of first insulation film and third insulation film is larger than the band gap of second insulation film. The third insulation film is polycrystal film including high dielectric constant material containing metallic element and oxygen. Fifth insulation film is polycrystal film including the same material as that for third insulation film. Fourth insulation film includes different material from that for third insulation film.

Abstract: The semiconductor device includes, in plan view, a gate electrode having a first portion located on a side surface portion where a plurality of emitter regions are formed, and a gate electrode having a second portion located between the plurality of emitter regions. The second portion of the gate electrode has a length shorter than first portion in the direction from the main surface to the back surface of the gate electrode of the semiconductor substrate.

Abstract: In a semiconductor device including a plurality of memory regions formed of split-gate type MONOS memories, threshold voltages of memory cells are set to different values for each memory region. Memory cells having different threshold voltages are formed by forming a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a data region, and a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a code region, of different materials or different thicknesses.

Abstract: A power control circuit according to one embodiment includes an H-bridge circuit formed using a plurality of power transistors. The power transistors are respectively connected to current measurement circuits that measure currents flowing through the power transistors. Each of the power transistors includes a main emitter and a sense emitter through which a current corresponding to a current flowing through the main emitter flows. Each of the current measurement circuits measures a current flowing through each of the power transistors by using a current flowing through the sense emitter included in the power transistor. A control circuit controls the power transistors based on current values respectively measured by the current measurement circuits.

Abstract: The present embodiments allow multiphase buck controllers to be able to detect Power-on-Reset (POR) automatically and subsequently reboot the system and reconfigure the system as a single or multi-rail system. Some embodiments use an onboard bus that can communicate between controllers. In these and other embodiments, the system is able to recover automatically from a power failure afflicting any or all of the controllers. Embodiments are applicable to flexible plug-and-play modular digital buck regulation applications.

Abstract: Present implementations include an electronic device with a system processor (SP) region connectable to an SP, a primary device region connectable to a first electronic device, and a secondary device region disposed between the SP device region and the primary device region, and connectable to a second electronic device. Present implementations further include a debugger region including a debugger unit and disposed adjacent to the primary device region and the secondary device region.

Abstract: The power control device reliably disconnects the current path of the failed output transistor. In particular, the power control device includes output transistors, an output terminal, bonding wires connecting the output transistors to the output terminal, output transistor driving circuits controlling the output of the output transistors, and a failure detection circuit detecting the failure of the output transistors. When the failure detection circuit detects the failure of the output transistors and outputs the failure detection signals, the output transistor drive circuits control the outputs of the output transistors so that a larger current flows through the bonding wires than when the failure is not detected.

Abstract: A technique is provided which can facilitate management of data in a memory device in a semiconductor device including the memory device and a data processing device. The semiconductor device includes a first external terminal, a second external terminal, a data processing device, and a memory device. The semiconductor device further includes a first bus coupled between the data processing device and the memory device, a second bus coupled between the data processing device and the second external terminal, a third bus coupled to the first external terminal, and a control circuit coupled to the first bus and the third bus. The control circuit has a management function of the memory device using the third bus.

Abstract: An object of the present invention is to provide a technique of duplexing monitor circuits in which a common cause failure can be eliminated. A semiconductor device has: a first monitor circuit monitoring that temperature or voltage of the semiconductor device is within a normal operation range; and a second monitor circuit monitoring normal operation of the first monitor circuit. The first and second monitor circuits generate information of temperature or voltage on the basis of different principles.

Abstract: A processor device capable of raising a hit rate of branch destination prediction is provided. Every time a load instruction to a data cache is generated, an equivalent value judgment circuit judges accord/disaccord of present load data and previous load data from a corresponding line. In an N bit region, as history records, a judgment history record circuit records judgment results of N times by the equivalent value judgment circuit before a conditional branch instruction is generated. When the conditional branch instruction is generated, based on the history records in the N bit region, a branch prediction circuit predicts the same branch destination as the previous branch destination obtained by a previous execution result of the conditional branch instruction or a branch destination different from the previous destination. Further, the branch prediction circuit issues an instruction fetch direction of the predicted branch destination to a processor main-body circuit.

Abstract: A semiconductor device capable of enlarging a read margin of a memory cell and a method of surrounding a read of a memory are provided. The reference word line RWL is activated in a time division manner with respect to the plurality of word lines WL. The precharge circuit PRE applies the read potential VRD to the bit line BL, and the precharge circuit PRE flows the read current Icel from the selected memory cell MC and the read reference current Iref from the reference cell RC to the bit line BL in a time division manner. A detection currents Ird2a, Irr2a, each of which is a current proportional to the current flowing through the bitline BL, flows through the current detection line CDL.

Abstract: To provide a memory protection circuit and a memory protection method suitable for quick data transfer between a plurality of virtual machines via a common memory, according to an embodiment, a memory protection circuit includes a first ID storing register that stores therein an ID of any of a plurality of virtual machines managed by a hypervisor, an access determination circuit that permits the virtual machine having the ID stored in the first ID storing register to access a memory, a second ID storing register that stores therein an ID of any of the virtual machines, and an ID update control circuit that permits the virtual machine having the ID stored in the second ID storing register to rewrite the ID stored in the first ID storing register.

Abstract: The present disclosure starts up a three-phase motor in a stable manner. During a start-up operation of a brushless DC motor, a motor drive system detects the position of a particularly suitable rotor while the rotor is resting, and applies a drive current to two phases in accordance with the detected position of the rotor. A controller changes the time of drive current application in accordance with the magnitude of back electromotive force that is in a non-conducting phase and detected by a detector during drive current application.

Abstract: The present invention provides a semiconductor device having an integration type A/D converter capable of speeding up. The semiconductor device includes a Johnson counter 18 for transmitting a lower bit counter signal JC<3:0>, a lower bit latch circuit 11 for outputting a lower bit latch result signal by a lower bit counter signal JC<3:0> and a lower bit latch signal 14, a determination circuit 12 for outputting an upper bit latch signal 15 by a lower bit latch signal 14, a binary gray converter circuit 20 for transmitting an upper bit counter signal GR<n:3>, and an upper bit latch circuit 13 for outputting an upper bit latch result signal by an upper bit counter signal GR<n:3> and an upper bit latch signal 15.

Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.

Abstract: A semiconductor device includes a first insulating layer, an optical waveguide, a first slab portion, a second insulating layer, and a conductive layer. The optical waveguide is formed on the first insulating layer and has a first side surface and a second side surface. The first slab portion is adjacent to the first side surface. The second insulating layer is formed on the optical waveguide. The conductive layer is formed on the second insulating layer. The optical waveguide has a first conductivity type. The first slab portion has first portion, second portion and third portion. The first portion has a second conductivity type opposite to the first conductivity type. The second portion is located farther from the optical waveguide than the first portion and has a first conductivity type. The third portion is formed between the optical waveguide and the second portion and has the first conductivity type.

Abstract: The present invention provides both a margin of a discharge start voltage with respect to a power supply voltage and a margin of a clamp voltage with respect to a breakdown withstand voltage of an internal circuit. The semiconductor device according to the embodiment includes a first amplifier circuit for amplifying a detection signal and outputting a drive signa, a second amplifier circuit for feedback-amplifying the detection signal to be input to the first amplifier circuit, and a discharge element whose discharge capability changed according to the magnitude of the drive signal.

Abstract: The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.

Abstract: A semiconductor device capable of improving the efficiencies of communication systems is provided. The semiconductor device comprises: an open period in which reception of data or transmission is allowed; a clock generation circuit defining a close period in which transmission of data and reception are not allowed; and a TSN controller connected to the clock generation circuit and performing transmission of data or reception, wherein the TSN controller performs semiconductor device or reception at another time than open period.