Abstract: A semiconductor device includes a first insulating layer, an optical waveguide formed on the first insulating layer, a fixed charge layer formed on the first insulating layer such that the fixed charge layer covers the optical waveguide, and a second insulating layer formed on the fixed charge layer.

Abstract: The control system according to embodiments includes a switching element, a control unit controlling the conductive state of the switching element, and a first capacitor storing charge supplied to the control unit. The first capacitor and the control unit are connected with each other via the switching element.

Abstract: A second gate dielectric film material and a memory gate electrode material are formed on a semiconductor substrate. The memory gate electrode material and the second gate dielectric film material formed in a peripheral circuit forming region are removed, and a part of each of the memory gate electrode material and the second gate dielectric film material is left in the memory cell forming region. Thereafter, in a state that the semiconductor substrate in the memory cell forming region is covered with a part of each of the memory gate electrode material and the second gate dielectric film material, heat treatment is performed to the semiconductor substrate to form a third gate dielectric film on the semiconductor substrate located in the peripheral circuit forming region. Thereafter, a memory gate electrode and a second gate dielectric film are formed.

Abstract: DAC control logic for controlling a DAC for supplying a target voltage VTARGET to a switching converter is disclosed. The DAC logic comprises control logic which is configured, in response to DAC ramp-down, to decrement DAC input code supplied to the DAC in a series of steps. The DAC control logic is configured, for at least some of the steps during ramp down, to wait until at least one switching cycle has occurred in the switching converter before decrementing the DAC input code from a current value to a new value.

Abstract: A semiconductor device capable of executing fault injection test on a plurality of failure detection mechanism in a short time is provided. The semiconductor device 1 has a plurality of hierarchical modules and an error control module 100 for controlling errors in the plurality of hierarchical modules. Each hierarchical module has a safety mechanism to detect failures in the functions of the components that make up the hierarchical modules. The error control module 100 includes a status register 120 configured to record data indicative of the status of failure of each hierarchical module, and a fault injection function 110 that outputs an error signal to the status register 120 to perform fault injection test. The error signal is inputted into the safety mechanism via the status register 120.

Abstract: Limitations on memory access decrease the computing capability of related-art semiconductor devices during convolution processing in a convolutional neural network. A semiconductor device according to an aspect of the present invention includes an accelerator section that performs computation on a plurality of intermediate layers included in a convolutional neural network by using a memory having a plurality of banks capable of changing the read/write status on an individual bank basis. The accelerator section includes a network layer control section that controls a memory control section in such a manner as to change the read/write status assigned to the banks storing input data or output data of the intermediate layers in accordance with the transfer amounts and transfer rates of the input data and output data of the intermediate layers included in the convolutional neural network.

Abstract: Reliability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes a step of preparing a lead frame in which a plurality of device forming regions are arranged in a matrix, a die bonding step of mounting a semiconductor chip on each device region, a resin sealing step of individually covering each semiconductor chip with a sealing body, and a lead plating step of plating an outer portion of a lead exposed from the sealing body. Between the resin sealing step and the lead plating step, an inspection step for detecting defective products in the resin sealing step and a defective product removal step for removing a device region of defective products are provided.

Abstract: A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

Abstract: A semiconductor device including an IE-type trench gate IGBT requires to be improved in IE effect to reduce on voltage. The semiconductor device includes a trench gate electrode or a trench emitter electrode between an active cell region and an inactive cell region. The trench gate electrode and the trench emitter electrode are provided across the inactive cell region.

Abstract: In a semiconductor device including a lockstep function, conflicts of bus accesses by a plurality of processors are suppressed. The semiconductor device includes a first processor, a second processor for monitoring operation of the first processor in a first mode, first and second buses, first and second non-shared resources dedicated to either the first or second processor in a second mode, and a first selector for selecting a bus for transferring interface signals between the second processor and the selected bus. In a second mode in which the first and second processors execute different instructions, the first selector selects the second bus. In the second mode, the first non-shared resource is accessed by the first processor via the first bus and the second non-shared resource is accessed by the second processor via the second bus.

Abstract: A first amorphous film containing hafnium, oxygen and a first element such as zirconium is formed, a plurality of grains containing a second element different from any of hafnium, oxygen and the first element are formed on the first amorphous film, a second amorphous film made of the same material as the first amorphous film is formed on the plurality of grains and on the first amorphous film, and a metal film is formed on the second amorphous film. Thereafter, by performing heat treatment, the first amorphous film is crystallized to form a first orthorhombic ferroelectric film and the second amorphous film is crystallized to form a second orthorhombic ferroelectric film.

Abstract: A method of operating a hysteretic synthetic current-mode switching regulator is disclosed. In the switching regulator, PWM pulses (PWM) are generated by a PWM generator (20; FIG. 7) in dependence upon a ramp voltage (VR) which oscillates between upper and lower window voltages (VW+, VW?). The ramp voltage depends on a control voltage (VC) which depends on current (IL) through an inductor (6). The method comprise determining whether a period (T) equal to or greater than a given period (TREFRESH) has elapsed without a PWM pulse being generated, upon a positive determination, causing the ramp voltage to be pulled up to or above the upper window voltage (VW+) for a given duration (?T) and when said given duration has elapsed, causing the ramp voltage to decrease until a rising edge of a PWM pulse is generated.

Abstract: A monolithic integrated circuit for controlling a high-side switching element for a load using a bootstrap capacitor is disclosed. The integrated circuit comprises a first supply voltage input for receiving a first input supply voltage V1, a second supply voltage input for receiving a second, current-limited input supply voltage VCP, a voltage-sensing input for receiving a source voltage, a first output for providing a drive signal VG to the switching element, a second output for providing a charging signal VBS to a bootstrap capacitor, a pre-driver for generating the drive signal, the pre-driver having a voltage input and an output which is coupled to the first output, and a power supply control section comprising first and second switches. The first and second switches are arranged in series between the first input and the second output, the second input is coupled to a node between the first and second switches, and the second node is coupled to a voltage input of the pre-driver.

Abstract: In a semiconductor device, a semiconductor substrate includes a bulk layer, a buried oxide layer provided in at least a partial region on the bulk layer, and a surface single crystal layer on the buried oxide layer. An inductor is provided above a main surface side of the semiconductor substrate on which the surface single crystal layer is disposed. To increase a Q value of the inductor, a ground shield is an impurity region formed in the bulk layer below the inductor and below the buried oxide layer.

Abstract: To extend the transmission distance with the voltage supply source and improve the communication performance of PLCs Solution. The power supply circuit includes a step-down DC/DC converter to which a voltage supplied from the power line is input and to which an input voltage is stepped down and output, a step-up/down DC/DC converter to which a voltage output from the step-down DC/DC converter or a voltage supplied from the power line is input and to which the input voltage is stepped up or stepped down and output to the power line communication circuit, a switch circuit for connecting an input of the step-up/down DC/DC converter to an output of the step-down DC/DC converter or power line, a voltage monitoring circuit for monitoring a voltage supplied from the power line, and a control circuit for controlling connection of the switch circuit based on the voltage value of the voltage supplied from the power line.

Abstract: A semiconductor device capable of stabilizing an internal voltage is provided. According to one embodiment, the semiconductor device comprises a stabilized power supply circuit for generating a first voltage, a charge pump circuit for generating a second voltage different from the first voltage using the first voltage, the COUT2 including a comparison circuit for comparing the second voltage with a reference voltage, and a dummy load circuit controlled to be turned on or off in response to a comparison result signal COUT2 outputted from the comparison circuit, and the Dummy load circuit receives the comparison result signal COUT2 and is turned on for a predetermined period, whereby at least a part of a current IDD based on the first voltage flows into the dummy load circuit.

Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.

Abstract: Example implementations include obtaining charging power from a power source, obtaining a charging command, activating a trickle current to a battery, entering a first charging state in response to a condition that a voltage of the battery does not satisfy a deep discharge threshold, and entering a second charging state in response to a condition that a voltage of the battery satisfies a deep discharge threshold. Example implementations can further include supplying the trickle current in a burst to the battery in response to a condition that the voltage of the battery does not satisfy a fuel gauge threshold, upon entering the second charging state. Example implementations can further include supplying the trickle current continuously to the battery in response to a condition that the voltage of the battery satisfies the fuel gauge threshold, upon entering the second charging state.

Abstract: First, an offset spacer including a stacked film of insulating films is formed on the upper surface of the semiconductor layer, the side surface of the gate electrode, and the side surface of the cap film. Next, a part of the insulating films is removed to expose the upper surface of the semiconductor layer. Next, in a state where the side surface of the gate electrode is covered with the insulating films, an epitaxial layer is formed on the exposed upper surface of the semiconductor layer. Here, among the offset spacers, the insulating film which is a silicon nitride film is formed at a position closest to the gate electrode, and the position of the upper end of the insulating film formed on the side surface of the gate electrode is higher than the position of the upper surface of the gate electrode.

Abstract: A pulse signal generator suitable for generating a two-phase pulse signal required as information of a rotation angle of a motor from a motor control device is provided. According to an embodiment, the pulse signal generator includes: a compensation unit that outputs a compensation signal for compensating for the deviation between the angle information representing the rotation angle of the rotor provided in the resolver and the fed back angle information; a counter pulse output unit that outputs a counter pulse having a frequency corresponding to the compensation amount of the compensation signal and code information representing the sign of the compensation signal, and a pulse processing unit that outputs a count value by a counter as the angle information, which counts the pulse according to the code information, the pulse processing unit generating two-phase pulse signals PA and PB using the values of the counter.