Abstract: One or more embodiments relate to a circuit that can be used to prevent cross conduction in an SMPS including multiple half-bridge modules connected in parallel to a single output inductor and driven by a single pulse width modulation (PWM) signal. According to certain aspects, each high-side driver and low-side driver in a single half-bridge module is synchronized in their switching with corresponding high-side drivers and low-side drivers in other half-bridge modules.

Abstract: An illegal address access blocking circuit includes a first register and a second register to set upper and lower limit values of an address range within which access to an external device is allowed. A first comparator compares a first value and the upper limit value, and outputs a high level signal when the first value is larger than the upper limit value. A second comparator compares the first value and the lower limit value, and outputs a low level signal. A first and logic circuit holds a logic sum of the high and low level signals, and outputs the logic sum as a third output, and a second logic circuit compares a fourth value inputted to a first request control line and the third output, and outputs a result of the comparison to a second request control line.

Abstract: A display control device comprises an output unit that outputs an inverted polarity of an AC signal in a constant cycle, based on a signal of the constant cycle; a stop control unit that stops the reversal of the polarity of the AC signal in the output unit, based on a stop signal; a rewrite control unit for outputting a display data rewrite signal; and a transmission control unit for controlling the rewrite control unit. The stop signal stops the reversal of the polarity of the AC signal during a period in which the display data rewrite signal is output. The AC signal stopped by the stop signal maintains a polarity before the stop of polarity reversal. The output unit inverts and outputs the polarity of the AC signal, based on the signal of the constant cycle, after a period in which the display data rewrite signal is output.

Abstract: An image encoding device includes an encoding circuit configured to encode an image, the image being constituted of a plurality of columns and a plurality of rows of which width are longer than the columns, generate a reference image and stores the reference image into a memory, and output a bit stream including the encoded image. The image encoding device also includes an image rotation circuit configured to rotate the image read from the memory by 90° and output the rotated image to a encoding processing circuit, and a read address generating circuit configured to read the column of the image from the memory, and provide the column with the image rotation circuit.

Abstract: A semiconductor device includes a first insulating layer, an optical waveguide, a first slab portion, a second insulating layer, and a conductive layer. The optical waveguide is formed on the first insulating layer and has a first side surface and a second side surface. The first slab portion is adjacent to the first side surface. The second insulating layer is formed on the optical waveguide. The conductive layer is formed on the second insulating layer. The optical waveguide has a first conductivity type. The first slab portion has first portion, second portion and third portion. The first portion has a second conductivity type opposite to the first conductivity type. The second portion is located farther from the optical waveguide than the first portion and has a first conductivity type. The third portion is formed between the optical waveguide and the second portion and has the first conductivity type.

Abstract: A hybrid-bonding-type solid-state imaging device is provided that prevents moisture from entering through the bonded interface and other areas. The solid-state imaging device includes a first interconnect structure over a sensor substrate and a second interconnect structure over a logic substrate, and the first and second interconnect structures are bonded together. At the bonded surface between the first and second interconnect structures, bonding pads formed in the first interconnect structure are bonded to bonding pads formed in the second interconnect structure. Eighth layer portions of a first seal ring formed in the first interconnect structure are bonded to eighth layer portions of a second seal ring formed in the second interconnect structure.

Abstract: A semiconductor device includes first and second voltage control lines for a first memory block and third and fourth voltage control lines for a second memory block, for driving gate lines for memory transistors; a first decoder driving the first and third voltage control lines; a second decoder driving the second and fourth voltage control lines; and a control circuit controlling a voltage for the first and second decoders. The control circuit supplies a first voltage and a second voltage lower than the first voltage to the first decoder and a third voltage between the first and second voltages, and the second voltage to the second decoder, before writing operation; and supplies the first voltage and the third voltage to the first decoder and a fourth voltage between the third and second voltages, and a fifth voltage lower than the second voltage to the second decoder, in the writing operation.

Abstract: method of manufacturing a semiconductor device capable of manufacturing a miniaturized semiconductor device is provided. The method of manufacturing a semiconductor device according to an embodiment includes the steps of: preparing a semiconductor substrate having a first surface and a second surface which is an opposite surface of the first surface; forming a hard mask having an opening on the first surface; forming a gate trench extending toward the second surface on the first surface using the hard mask as a mask; widening the width of the opening; filling the opening with an interlayer insulating film; and forming a contact hole in the interlayer insulating film by removing the hard mask.

Abstract: The present invention provides a semiconductor device enabling efficient compression without increasing the circuit size and a processing method using the semiconductor device. According to an embodiment, an image processor includes: a coding circuit to perform image processing on a target image divided into a plurality of tiles, the image processing being performed on each of the tiles; a determination circuit to determine whether a tile boundary is included in the area of an image block serving as a unit of compression of the target image; and a compression circuit to compress the image block image-processed by the coding circuit, according to a determination result of the determination circuit.

Abstract: In the semiconductor device, a first defect formation preventing film is formed on the first wiring side, and a second defect formation preventing film is formed on the second wiring side. when a ratio of an infrared absorption intensity corresponding to a bond between silicon and hydrogen to an infrared absorption intensity corresponding to a bond between silicon and oxygen is defined as an abundance ratio, the abundance ratio in the first defect formation preventing film is smaller than the abundance ratio in the second interlayer insulating film. The abundance ratio in the second defect formation preventing film is smaller than the abundance ratio in the second interlayer insulating film.

Abstract: This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.

Abstract: A mobile object control system has an SfM unit detecting distance to an object imaged by a monocular camera by using the SfM algorithm, a first-stop-position output unit outputting a first stop position, a second-stop-position calculating unit calculating a second stop position closer than the first stop position, and a control unit controlling travel of a mobile object. The control unit controls the mobile object so as to stop at the second stop position. When a predetermined starting condition is satisfied, the control unit controls the mobile object so as to start. The SfM unit detects the distance to an object by using an image captured by the monocular camera after the mobile object starts. When a result of detection of the distance of the object by the SfM unit is obtained, the control unit uses the detection result for control of the travel.

Abstract: Present implementations include an electronic device with a system processor (SP) region connectable to an SP, a primary device region connectable to a first electronic device, and a secondary device region disposed between the SP device region and the primary device region, and connectable to a second electronic device. Present implementations further include a debugger region including a debugger unit and disposed adjacent to the primary device region and the secondary device region.

Abstract: A switch group selectively outputs a signal input from IC terminals and a reference voltage. Another switch group selectively outputs a signal input from IC terminals and a reference voltage. A differential amplifier amplifies a differential voltage between a signal output from the switch group and a signal output from the another switch group. The switch group and the another switch group include the same number of switches. When to select any of signals input from the IC terminals in the switch group, a reference voltage is selected in the another switch group. When to select any of signals input from the IC terminals in the another switch group, a reference voltage is selected in the switch group.

Abstract: Debugging a program in an apparatus using a lockstep method are more efficiently performed and a semiconductor apparatus includes a first processor core, a second processor core, a first debug circuit, a second debug circuit, and an error control circuit capable of outputting an error signal for stopping execution of a program by the first processor core and the second processor core. The second debug circuit performs setting regarding debugging different from that of the first processor core with respect to the second processor core. Even if a first processing result of the first processor core and a second processing result of the second processor core do not coincide with each other, the error control circuit invalidates the output of the error signal when the first processor core executes the program and the second processor core stops execution of the program based on the setting regarding debugging.

Abstract: A semiconductor device capable of improving operating margins is provided. The semiconductor device comprises a memory circuit including a memory cell comprised of a SOTB transistor, and a mode designation circuit switching operation modes of the memory circuit for a first mode or a second mode. The memory circuit includes a substrate bias generation circuit supplying a substrate bias voltage to the SOTB transistor and a timing signal generation circuit generating a timing signal used for a reading operation or a writing operation of the memory circuit. The substrate bias generation circuit does not supply the substrate bias voltage to the SOTB transistor in the second mode.

Abstract: A method and apparatus for implementing power modes in microcontrollers (MCUs) using power profiles. In one embodiment of the method, a central processing unit (CPU) of the MCU executes a first instruction for calling a subroutine stored in a memory of the MCU, wherein the first instruction comprises a first parameter to be passed to the subroutine. Thereafter the CPU writes a first value to a first special function register (SFR) of the MCU in response to executing the first instruction, wherein the first value is related to the first parameter. The MCU operates in a first power mode in response to the CPU writing the first value to the first SFR. The CPU also executes a second instruction for calling the subroutine, wherein the second instruction comprises a second parameter to be passed to the subroutine. In response the CPU writes a second value to a second SFR of the MCU in response to executing the second instruction, wherein the second value is related to the second parameter.

Abstract: In order to correct the rotation angle value without an increase in the circuit size, a rotation period measurement unit measures a rotation period of a rotary shaft in which a rotation angle is detected by using a resolver that outputs a signal corresponding to the rotation angle of the rotary shaft. A rotation speed calculation unit calculates the rotation speed of the rotary shaft based on the rotation period. An acceleration calculation unit calculates the rate of change of the rotation speed per interval when a given rotation angle of the rotary shaft is divided into 2n+1 intervals, in which n is an integer of 1 or more. An estimated angle calculation unit calculates the rotation angle estimation value, assuming that the rotary shaft performs a uniform acceleration motion, based on the rotation speed and the rate of change of the rotation speed. A correction value calculation unit calculates the correction value of the rotation angle value converted from the output signal of the resolver.

Abstract: A semiconductor device capable of detecting whether test operation is normal is provided. The semiconductor device includes a plurality of memory cells arranged in a matrix, a plurality of word lines provided corresponding to each of the rows of the plurality of memory cells respectively, a decoder for generating driving signals for driving the plurality of word lines, and a detection circuit provided between the plurality of word lines and the decoder for simultaneously raising the plurality of word lines by test operation and detecting whether or not the rising state of the plurality of word lines is normal.

Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.