Abstract: A polycrystalline silicon resistor is large in coefficient of fluctuation in resistance between before and after the completion of a package molding process. To enable highly accurate trimming, it is desired to implement a resistor that is hardly subjected to stress produced in a substrate during a package molding process. A resistance element is formed of a plurality of wiring layers and has a repetitive pattern of a first conductive layer formed in a first wiring layer, a second conductive layer formed in a second wiring layer, and an interlayer conductive layer coupling the first conductive layer and the second conductive layer together.

Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.

Abstract: A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.

Abstract: An impedance measuring semiconductor circuit that measures impedance of a specimen. The impedance measuring semiconductor circuit includes an operational amplifier, a resistance coupled between a negative input terminal and an output terminal of the operational amplifier, a D/A converter coupled to a positive input terminal, a switch; an A/D converter that is coupled with the output terminal of the operational amplifier and a one-side terminal of a specimen and measures an output voltage from the operational amplifier and a one-side terminal voltage, and a controller that controls an output voltage from the D/A converter based on a one-side terminal voltage measured by the A/D converter.

Abstract: Provided is a semiconductor device which can perform secure data transmission/reception considering functional safety. The semiconductor device includes a hardware security module circuit which performs an authentication process and an error detection circuit used to perform an error detection process at least on first data which is processed in the hardware security module circuit. A memory area associated with the error detection circuit is configured to be accessible only by the hardware security module circuit when the error detection process is performed at least on the first data.

Abstract: The semiconductor device includes a first semiconductor substrate, a first wiring layer, a second wiring layer, a second semiconductor substrate, a first conductive portion, and a second conductive portion. The first wiring layer includes a first electrode pad and a first inductor electrically connected with each other. The second wiring layer includes a second inductor and a second electrode pad electrically connected with each other. The first conductive portion is formed in the second semiconductor substrate, the second wiring layer, and the first wiring layer so as to reach the first electrode pad from the back surface of the second semiconductor substrate. The second conductive portion is formed in the second semiconductor substrate and the second wiring layer so as to reach the second electrode pad from the back surface of the second semiconductor substrate. The first inductor and the second inductor are disposed so as to face each other.

Abstract: The semiconductor device according to this disclosure includes an analog input terminal, an amplifier circuit, a sample-and-hold circuit, an analog input switch connected between the analog input terminal and the input terminal of the amplifier circuit, a control switch connected between the output terminal of the amplifier circuit and the input terminal of the sample-and-hold circuit, a comparison circuit connected to the output terminal of the sample-and-hold circuit, an analog-to-digital converter connected to the comparator circuit, a control circuit, and a signal conversion circuit for converting the first control signal from the control circuit into a second control signal. The analog input switch is turned on during the activation level of the second control signal. The period of the activation level of the second control signal is longer than that of the first control signal to reduce a conversion error of an analog-to-digital conversion circuit.

Abstract: The terminal pattern TP1 of the wiring substrate PB has a side T1a facing the terminal pattern TP2 and the terminal pattern TP2 of the wiring substrate PB has a side T2a facing the side T1a of the terminal pattern TP1. The side T1a and the side of T2a are exposed from the opening portion OP1 and OP2 of the solder resist layer SR1 respectively, and outer peripheries of terminal patterns TP1 and TP2 other than sides T1a and T2a are not exposed from opening portions OP1 and OP2. The opening portion OP1 and the opening portion OP2 are separated from each other. The electrode E1 of the capacitor C1 is soldered to the terminal pattern TP1 exposed from the opening portion OP1, and the electrode E2 of the capacitor C1 is soldered to the terminal pattern TP2 exposed from the opening portion OP2.

Abstract: Provided are a semiconductor device capable of preventing erroneous operation and providing a field plate effect, and a method of manufacturing the semiconductor device. In a diode, a gate electrode, a p+ source region, and an n-type body region are electrically coupled to one another. A contact region is disposed between the n-type body region and the p+ source region in a first surface of a semiconductor substrate.

Abstract: A chip mounting portion included in a semiconductor device has a region including a semiconductor chip in plan view. When an average surface roughness of the region is “Ra”, 0.8 ?m?Ra?3.0 ?m holds.

Abstract: In a semiconductor device and an information processing system according to one embodiment, an external device generates external device unique information by using a unique code which is a value unique to the semiconductor device, and generates second information by encrypting the first information with the use of the external device unique information. The semiconductor device stores the second information and generates the principal device unique information independently of the external device, with the use of the unique code of the semiconductor device holding the second information, and decrypts the second information with the use of the principal device unique information to obtain the first information.

Abstract: A semiconductor device includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

Abstract: A semiconductor device includes: a plurality of first sensors that is arranged at predetermined intervals; a first measurement circuit that measures the added value of two or more first detection signals among those output from all the first sensors and outputs a first measurement result; a second measurement circuit that measures the added value of two or more first detection signals that are different from those measured by the first measurement circuit among the first detection signals and outputs a second measurement result; and an analysis circuit that analyzes the position of a detection target on the basis of the first and second measurement results, wherein the first sensors and the first and second measurement circuits are coupled to each other so that combinations of the first and second measurement results differ from each other depending on the position of the detection target.

Abstract: Example implementations include a bandgap voltage device with a first current source operatively coupled to a bandgap input node and a bandgap output node and operable to output a first proportional-to-absolute-temperature (PTAT) current, a current mirror including a first bandgap transistor and a second bandgap transistor, and operatively coupled to the bandgap output node, and a second current source operatively coupled to the current mirror and operable to output a second PTAT current.

Abstract: Apparatus for performing offset cancellation is disclosed. The apparatus comprises a gating circuit (6) for receiving an analogue signal (3) from a source (2) and providing a gated analogue signal (9) to an analogue circuit (10), a gating controller (7; 14; FIG. 1) and a digital processor (14; FIG. 1) for receiving a digital signal (13) converted from an analogue output (11) from the analogue circuit (10). The gating circuit comprises at least one path (211), each path respectively comprising, an input terminal (221), an output terminal (231), a node (241) interposed between the input and output terminals, a first transistor (Q1) having a channel arranged between the input terminal and the node, and a second transistor (Q3) having channel arranged between the node and a fixed reference, such as ground (GND).

Abstract: A TCAM (Ternary Content Addressable Memory) according to the embodiment includes repeaters in a delay path for controlling the timing in the replica circuit that defines the timing of matching. According to the above configuration, the TCAM which consumes low power and operates at high speed can be realized.

Abstract: A license managing method including an execution device that executes software and a software storage device coupled to the execution device further includes a license storage device that stores license information indicating the number of licenses for permitting a license of the software, and the license managing method includes the step of license-managing of controlling storage of the software to be downloaded into the software storage device or execution of the software by the execution device based on the license information stored in the license storage device when the software whose license permission is required is downloaded.

Abstract: There is a need to provide a semiconductor device that improves an interrupt capability of a virtual machine. A semiconductor device includes a memory to store a plurality of virtual machines and a virtual machine manager to manage the virtual machines and a CPU to perform the virtual machines and the virtual machine manager. The CPU causes an active virtual machine to perform an interrupt process when information (first information) about an interrupt-processing virtual machine is equal to information (second information) about the active virtual machine. When the first information differs from the second information, the CPU causes the virtual machine manager to stop the active virtual machine and operates the interrupt-processing virtual machine to perform an interrupt process.

Abstract: A semiconductor device comprising: a semiconductor chip; and a wiring substrate having: a first region overlapping with the semiconductor chip, and a second region surrounding the first region in plan view. Also, the wiring substrate includes: a first wiring layer, a third wiring layer, and a plurality of data wirings arranged so as to straddle a border between the first region and the second region. Also, the plurality of data wirings includes: a first data wiring transmitting a first byte data signal, and a second data wiring transmitting a second byte data signal. Also, in the first wiring layer, the first data wiring is arranged so as to straddle the border. Also, in the third wiring layer, the second data wiring is arranged so as to straddle the border. Further, in plan view, the first data wiring and the second data wiring are overlapped with each other.

Abstract: A semiconductor device include a semiconductor substrate, a first trench electrode formed in the semiconductor substrate and having a first portion, a second trench electrode formed in the semiconductor substrate having a second portion facing the first portion, a floating layer of a first conductivity type formed around the first and second trench electrodes, a drift layer of a second conductivity type connected to the floating layer of the first conductivity type and formed between the first and second trench electrodes, an impurity layer of the first conductivity type connected to the drift layer of the second conductivity type and formed between the first and second trench electrodes, and a floating layer control gate having a portion located at least above the impurity layer of the first conductivity type.