Abstract: Existing semiconductor devices cannot detect a failure occurring in a circuit required for mode switching processing for other than arithmetic cores, so that reliability is inadequate. A semiconductor device of an embodiment of the invention includes: a selector which is provided corresponding to among plural arithmetic cores one used as a checking arithmetic core in lock-step mode and which, in lock-step mode, blocks the interface signals outputted from the corresponding arithmetic core and, in split mode, lets the interface signals outputted from the corresponding arithmetic core through; an access monitor which monitors the interface signals outputted via a selector and, when an abnormal state of the interface signals is detected, outputs an error signal; and an error control unit which outputs, based on the error signal outputted from the access monitor, an abnormal state processing request to a higher-order system.

Abstract: According to an aspect of a present invention, there is provided a semiconductor device including a first power monitoring device and a second power monitoring device. The first power monitoring device outputs first operating power that is to be supplied to a second control section. The second power monitoring device outputs second operating power that is to be supplied to a first control section. Based on a first setting given from the first control section, a first power monitoring circuit autonomously verifies whether the second operating power is normal, and periodically transmits the result of verification to the second control section as first error information. Based on a second setting given from the second control section, a second power monitoring circuit autonomously verifies whether the first operating power is normal, and periodically transmits the result of verification to the first control section as second error information.

Abstract: The present invention provides a semiconductor device that can reduce the power consumption, including: a plurality of search memory cells arranged in a matrix; a plurality of match lines provided corresponding to each memory cell row to determine match/mismatch between data stored in the search memory cell and search data; a plurality of match line retention circuits provided corresponding to each of the match lines; a storage unit for storing information relating to the state of each of the match lines; and a selection circuit for selectively activating the match line retention circuits based on the information stored in the storage unit.

Abstract: A semiconductor device includes a plural search memory cells, a plural match lines, a plural sub-ground lines, and a plural amplifiers. The search memory cells are disposed in a matrix form. The match lines are disposed in association with respective memory cell rows and used to determine whether search data matches data stored in the search memory cells. The sub-ground lines are disposed in association with respective memory cell rows. The amplifiers are disposed in association with respective memory cell rows to amplify the potentials of the match lines. The match lines and the sub-ground lines are respectively precharged to a first potential and a second potential before a data search. When the search data is mismatched, the match lines are electrically coupled to associated sub-ground lines through the search memory cells and set to an intermediate potential that is intermediate between the first potential and the second potential.

Abstract: A semiconductor device includes an output driving circuit configured to output an output current to an output terminal; a detection resistor connected between the output terminal and the output driving circuit; an amplification unit configured to output an analog detection signal generated by amplifying a voltage between both ends of the detection resistor; a current generation circuit configured to output a reference current; a reference resistor connected between the current generation circuit and a ground and configured to output a reference voltage according to the reference current; an A/D converter configured to convert the analog detection signal into a digital detection signal using the reference voltage as a reference; and a control circuit configured to control the output current output from the output driving circuit according to the digital detection signal. The detection resistor has a same temperature characteristics as the reference resistor.

Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small.

Abstract: There is a need to provide a semiconductor device, a semiconductor system, and a semiconductor device manufacturing method capable of accurately monitoring a minimum operating voltage for a monitoring-targeted circuit. A monitor portion of a semiconductor system according to one embodiment includes a voltage monitor and a delay monitor. The voltage monitor is driven by power-supply voltage SVCC different from power-supply voltage VDD supplied to an internal circuit as a monitoring-targeted circuit and monitors power-supply voltage VDD. The delay monitor is driven by power-supply voltage VDD and monitors signal propagation time for a critical path in the internal circuit. The delay monitor is configured so that a largest on-resistance of on-resistances for a plurality of transistors configuring the delay monitor is smaller than a largest on-resistance of on-resistances for a plurality of transistors configuring the internal circuit.

Abstract: Disclosed is a semiconductor device in which an internal voltage fluctuation when a current jump occurs is restrained. The semiconductor device includes a plurality of blocks, each of which performs a given operation, and a current jump control circuit. The current jump control circuit monitors control signals in each of the blocks and calculates predicted values of consumption current of the blocks, based on results of monitoring at different timings, thereby controlling a fluctuation of consumption current of the blocks. The current jump control circuit controls operation of a subset or all of the blocks, if an increase of a predicted value of consumption current of the blocks is larger than a first value or a decrease of the predicted value is larger than a second value.

Abstract: A semiconductor device which can secure a high breakdown voltage and to which a simplified manufacturing process is applicable and a method for manufacturing the semiconductor device are provided. An n+ buried region has a floating potential. An n-type body region is located on a first surface side of the n+ buried region. A p+ source region is located in the first surface and forms a p-n junction with the n-type body region. A p+ drain region is located in the first surface spacedly from the p+ source region. A p-type impurity region PIR is located between the n+ buried region and the n-type body region and isolates the n+ buried region and the n-type body region from each other.

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Abstract: A conventional analog-to-digital conversion circuit has a problem that conversion errors cannot be suppressed.

Abstract: An SOI substrate is attracted to and detached from an electrostatic chuck included in a semiconductor manufacturing device without failures. A semiconductor device includes a semiconductor substrate made of silicon, a first insulating film formed on a main surface of the semiconductor substrate and configured to generate compression stress to silicon, a waveguide, made of silicon, formed on the first insulating film, and a first interlayer insulating film formed on the first insulating film so as to cover the waveguide. Further, a second insulating film configured to generate tensile stress to silicon is formed on the first interlayer insulating film and in a region distant from the optical waveguide by a thickness of the first insulating film or larger. The second insulating film offsets the compression of the first insulating film.

Abstract: A semiconductor device includes: a cell region provided in a main surface of a semiconductor substrate composed of a crystal plane (100); a field insulating film embedded in the semiconductor substrate; and an annular p-type well region surrounding the cell region. The p-type well region includes a first region extending in a <010> direction, a second region extending in a <001> direction, and a third region connecting the first region and the second region and having an arc shape in plan view. The field insulating film has an opening provided in the p-type well region and extending along the p-type well region in plan view. The opening includes a first opening extending in the <010> direction in the first region and a second opening extending in the <001> direction in the second region, and the first opening and the second opening are divided from each other in the third region.

Abstract: The semiconductor device includes a first inverter and a second inverter which is connected thereto in series. Each of the first and the second inverters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the second inverter is smaller than the number of the projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the first inverter.

Abstract: A conventional power supply device has a problem in miniaturization. A power supply device generates a prediction value of an error signal from first and second error signals, and controls an output voltage so that the prediction value lies between first and second threshold values. The first error signal is obtained by converting an error voltage based on the difference between the output voltage and a reference voltage at a first timing. The second error signal is obtained by converting an error voltage based on the difference between the output voltage and the reference voltage at a second timing.

Abstract: A phase shifter capable of improving phase accuracy by a simple method is provided. The phase shifter includes a hybrid coupler circuit including inductors with mutual inductances, an amplifying circuit, an impedance matching circuit provided between the hybrid coupler circuit and the amplifying circuit. The impedance matching circuit includes a first resistance element connected to an output node of the hybrid coupler circuit, a capacitance element connected between the first resistance element and the ground line in series, another inductor connected in parallel with the first resistance element, and a second resistance element provided between the inductor and the ground line in series.

Abstract: An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.

Abstract: In a semiconductor device having a variable gain amplifier, a setting error of a gain associated with a crosstalk noise is reduced. A switch block included in the variable gain amplifier includes a plurality of switch transistors Mp1, Mp2, MN1, and Mn2, and can variably set the parallel number of the switches used for coupling by selecting a forward coupling state for coupling the common wirings CSP, CSN to output wirings OUTP, OUTN, respectively, or a cross coupling state for coupling to OUTN, OUTP, respectively. Output wirings OUTN, OUTP form an output wiring pair by extending in a X direction while crossing each other through an underlying wiring layer ML[x-1]. At least one of the common wirings CSP, CSN is located next to the output wiring pair in a Y direction.

Abstract: A voltage monitoring module including a first input terminal coupled to a high-voltage-side terminal of a battery cell through a first path including an external resistor, a first terminal coupled to the high-voltage-side terminal of the battery cell through a second path; a first switch coupled to the first input terminal, a second switch coupled to the first terminal; a second input terminal and a second terminal coupled to a low-voltage-side terminal of the battery cell, a third switch that is coupled to the second input terminal; a fourth switch that is coupled to the second terminal, and a control circuit that controls ON/OFF of the first through fourth switches, wherein an element that suppresses fluctuation of a voltage input to the first switch through the first input terminal that is coupled between the first switch and a fixed voltage.