Abstract: A semiconductor device includes a plurality of IP cores, a plurality of storage devices, a configuration information acquiring unit that acquires configuration information for specifying a timing when the IP core accesses the storage device, and an allocation determining unit that determines the storage device allocated to the IP core. The configuration information acquiring unit acquires configuration information regarding a first IP core and configuration information regarding a second IP core. The allocation determining unit determines, based on the configuration information, whether an access timing by the first IP core is the same as an access timing by the second IP core, and when it is determined that the access timings are the same, determines allocation in such a way that the storage device allocated to the first IP core becomes different from the storage device allocated to the second IP core.

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface, a first insulation isolation film in which a first trench is formed and a conductive film having a gate electrode, a first buried part buried in the first trench and a first cap part located on the first buried part. The semiconductor substrate has a source region, a drain region, a drift region and a body region. The gate electrode faces the body region which is sandwiched between the drift region and the source region while being insulated from the body region. The first cap part projects longer than the first buried part in a channel width direction which is a direction along a boundary between the body region and the drift region in a planar view on the first insulation isolation film.

Abstract: A memory circuit includes: a control circuit generating first and second start signals within a single signal cycle of an input clock signal; an address control circuit coupled to a plurality of address ports for receiving a plurality of address signals and activating one of word lines corresponding to one of the address signals based on the first or second start signals; and a data input/output circuit for writing or reading data by selecting one of memory cells coupled to the activated word line. The control circuit includes: a start signal generation unit that generates the first start signal in response to a first pulse signal and the second start signal in response to a second pulse signal, and a pulse signal generation unit that generates the first pulse signal in response to the input clock signal and the second signal in response to the first start signal.

Abstract: A differential mixer and a method which can reduce a leak component of a local oscillation differential signal are provided. A differential mixer includes a mixer core unit to which a high frequency signal and a local oscillation differential signal are inputted and which outputs an intermediate frequency differential signal, a common feedback unit which applies a bias voltage to a signal electrically coupled to the high frequency signal and to which a common voltage is fed back from the intermediate frequency differential signal, and a bias unit that applies a reference voltage to the common feedback unit. The common feedback unit generates the bias voltage based on the reference voltage. The bias unit controls the reference voltage so that a leak component of the local oscillation differential signal is a predetermined value or less at an output end of the intermediate frequency differential signal.

Abstract: A drawing processing device includes a GPU, a diagnosis circuit which executes divisions of a diagnostic test of the GPU and a control unit which controls execution of the divided diagnostic tests by the diagnosis circuit. The control unit schedules so as to complete execution of drawing processes for one frame in a first time which is a one-frame display time which is defined in accordance with a frame rate and schedules so as to execute the divided diagnostic tests in a third time which is a remaining time obtained by subtracting a second time which is a processing time requested for execution of the drawing processes for one frame from the first time.

Abstract: A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.

Abstract: A semiconductor device includes a SRAM (Static Random Access Memory) circuit. The SRAM circuit includes a static memory cell, a word line coupled with the static memory cell, a pair of bit lines coupled with the static memory cell, a first interconnection coupled with the static memory cell, and supplying a first potential, a second interconnection coupled with the static memory cell, and supplying a second potential lower than the first potential, a first potential control circuit controlling a potential of the second interconnection, and a second potential control circuit controlling a potential of the first interconnection. The SRAM circuit includes, as an operation mode a first operation mode for reading data from the SRAM circuit, or for writing data into the SRAM circuit, and a second operation mode for reducing power consumption than the first operation mode.

Abstract: In one semiconductor chip, driving transistors, a current sensor, and a temperature sensor for sensing a temperature of a driver area are arranged in a driver area, and a current sensing circuit, an analog-digital converter, and a temperature sensor for sensing a peripheral circuit area are arranged in a peripheral circuit area. A correction circuit unit corrects a digital sensed voltage from the analog-digital converter based on a sensing result of the temperature sensor of the driver area and a sensed result of the temperature sensor of the peripheral circuit area.

Abstract: To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed.

Abstract: A plurality of transfer modules (402-0 to 402-M) that transfer data between processing units are provided so as to respectively correspond to a plurality of processing units (401-0 to 401-M). First ring buses (403-0 to 403-M) connect, for each of the processing units (401-0 to 401-M), subunits within a corresponding processing unit and the transfer module corresponding to the processing unit so that they form a ring shape. The plurality of transfer modules (402-0 to 402-M) are connected so that they form a ring shape by a second ring bus (404).

Abstract: Conventional image sensors cannot generate highly-accurate correction values in a short time.

Abstract: Related-art back bias generation circuits cause a problem where a long time is required for transition between an operating state and a standby state because driving power is lowered to reduce the power consumption in the standby state. A back bias generation circuit outputs a predetermined voltage. The predetermined voltage is the back bias voltage of a substrate in a standby mode. A bias control circuit stores an electrical charge while a circuit block is in an operating mode, supplies the stored electrical charge to the substrate of a MOSFET included in the circuit block when the circuit block transitions from the operating mode to the standby mode, and subsequently supplies the output of the back bias generation circuit to the substrate of the MOSFET.

Abstract: A semiconductor device of the present invention includes, in a region 1C, a top electrode made by a semiconductor layer of an SOI substrate, a capacitive insulating film made by an insulating layer, a bottom electrode made by a supporting board, and a lead part (a high-concentration impurity region of an n type) of the bottom electrode coupled to the supporting board. An SOI transistor in a region 1B is formed over a main surface of the semiconductor layer over the insulating layer as a thin film, and threshold voltage can be adjusted by applying a voltage to a well arranged on the rear face side of the insulating layer.

Abstract: An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. A plurality of first semiconductor chips and a second semiconductor chip which controls each of the plurality of first semiconductor chips are mounted side by side on a second wiring substrate of the semiconductor device. Further, the plurality of first semiconductor chips are mounted between a first substrate side of the wiring substrate and an extension line of a first chip side of the second semiconductor chip. Furthermore, the first wiring substrate includes a first power line which supplies a first power potential to each of the plurality of first semiconductor chips and a second power line which supplies a second power potential to the second semiconductor chip and has a width larger than that of the first power line.

Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

Abstract: An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A first memory cell includes a first control gate electrode and a first memory gate electrode which are formed over a semiconductor substrate to be adjacent to each other. A second memory cell includes a second control gate electrode and a second memory gate electrode which are formed over the semiconductor substrate to be adjacent to each other. A width of a sidewall spacer formed on a side of the second memory gate electrode opposite to a side thereof where the second memory gate electrode is adjacent to the second control gate electrode is smaller than a width of another sidewall spacer formed on a side of the first memory gate electrode opposite to a side thereof where the first memory gate electrode is adjacent to the first control gate electrode.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: A ring oscillator for detecting a characteristic degradation of MOSFETs is required to be highly sensitive to NBTI degradation or PBTI degradation. A semiconductor device comprises a ring oscillator and a delay detecting circuit which detects a delay through gate circuits based on the oscillation frequency of the ring oscillator. The ring oscillator comprises an input terminal to which an oscillation control signal is input, an output terminal which outputs an oscillation signal, an oscillation control gate circuit having a first input terminal which is coupled to the input terminal and a second input terminal to which a terminal different from the input terminal is coupled, NAND circuits, and NOR circuits. The NAND and NOR circuits are cascade coupled alternately, plural inputs of the NAND circuits and of the NOR circuits are coupled together, and drive power of the NAND circuits differs from drive power of the NOR circuits.

Abstract: A semiconductor device includes: a plurality of first wires formed in a first layer and indicating fixed potentials; and an inductor formed in a second layer stacked on the first layer, and wiring widths of the first wires located within a range of a formation region of the inductor in a plan view among the plurality of first wires are formed narrower than wiring widths of the first wires located outside the range of the formation region of the inductor.

Abstract: An object of the present invention is to provide a power supply voltage stabilizing method that can suppress the performance of a switching power supply from being deteriorated even when a battery voltage varies and/or load conditions change. In a power supply voltage stabilizing method of a switching power supply including an output power MOS to which a battery voltage is supplied and a PWM feedback control unit that controls the output power MOS, the PWM feedback control unit includes a voltage feedback controller that controls on the basis of a power supply voltage output from the switching power supply and a current feedback controller that controls on the basis of a current output from the switching power supply. A variation in the battery voltage and/or a change in the load condition of the switching power supply are/is detected, and the bandwidth of the PWM feedback control unit is dynamically changed in accordance with the result of the detection.