Patents Assigned to RENESAS
  • Semiconductor device and power control device
    Patent number: 10396547
    Abstract: To realize a reduction in the number of parts in a system including a driver IC (semiconductor device). A high potential side power supply voltage is applied to a power supply application area. A high side area is formed with a circuit which includes a driver driving a high side transistor and is operated at a boot power supply voltage with a floating voltage as a reference. A low side area is formed with a circuit operated at a power supply voltage with a low potential side power supply voltage as a reference. A first termination area is disposed in a ring form so as to surround the power supply application area. A second termination area is disposed in a ring form so as to surround the high side area.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: August 27, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryo Kanda, Hiroshi Kuroiwa, Tetsu Toda, Yasushi Nakahara
  • Method for manufacturing semiconductor device
    Patent number: 10395967
    Abstract: Provided is a method of manufacturing a semiconductor device with improved manufacturing efficiency for the semiconductor device. The method of manufacturing a semiconductor device includes the steps of: (a) forming a circuit at a front surface side of a wafer (semiconductor wafer) having the front surface and a back surface opposite to the front surface; (b) grinding the back surface of the wafer that has a center part (first part) and a peripheral edge part (second part) surrounding a periphery of the center part in such a manner that the center part is thinner than the peripheral edge part; (c) attaching an upper surface (bonding surface) of a holding tape to the front surface of the wafer; and (d) separating the center part from the peripheral edge part by cutting a part of the center part with a blade (rotary blade) while the wafer is held by the first tape.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 27, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takamitsu Yoshihara, Takahiro Kainuma, Hiroi Oka
  • Semiconductor device
    Patent number: 10396549
    Abstract: Provided is a semiconductor device making it possible to promote area reduction while maintaining ESD resistance. The semiconductor device includes a power wire, a ground wire and a protection circuit provided between the power wire and the ground wire so as to cope with electrostatic discharge. The protection circuit includes a first transistor, a first resistive element, a second transistor, a first capacitive element, a first inverter and a protection transistor. A gate width of the second transistor is narrower than a gate width of the first transistor.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 27, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masashi Arakawa, Tadashi Fukui, Koji Takayanagi
  • SEMICONDUCTOR DEVICE
    Publication number: 20190259443
    Abstract: A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 22, 2019
    Applicant: Renesas Electronics Corporation
    Inventor: Koji NII
  • Manufacturing method for semiconductor device and semiconductor device
    Patent number: 10388597
    Abstract: A die bonding process for assembling a semiconductor device includes the steps of applying a sintered-silver-use paste to each of a plurality of first regions on an upper surface of a chip mounting part, drying the sintered-silver-use paste and applying a silver paste to a second region located between/among the respective first regions. Further, the process includes the step of mounting a semiconductor chip onto the chip mounting part in such a manner that a rear surface of the semiconductor chip faces an upper surface of the chip mounting part with the sintered-silver-use paste and the silver paste being interposed. After mounting the chip, part of each of first, second, third and fourth corners of a principal surface of the semiconductor chip is located in each of the first regions.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: August 20, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masatoshi Sugiura, Hiroi Oka
  • Semiconductor device
    Patent number: 10388366
    Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: August 20, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinji Tanaka, Makoto Yabuuchi, Yuta Yoshida
  • Semiconductor device, electronic apparatus, and image processing method
    Patent number: 10387995
    Abstract: A semiconductor device 1 includes an image input unit 11 and an image output unit 12. The image input unit 11 receives first image data from a camera 91 and outputs second image data to a memory unit 93 through a shared bus 130. The image output unit 12 receives the second image data stored in the memory unit 93 through the shared bus 130 and outputs third image data to a monitor 92. The third image data is generated by performing an affine-conversion on the first image data. Magnification processing in the affine-conversion is not performed in the image input unit 11. In this way, it is possible to provide an excellent semiconductor device suitable for image processing or the like.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: August 20, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Akihiro Yamamoto, Hiroyuki Hamasaki
  • Semiconductor device and method for manufacturing the same
    Patent number: 10388660
    Abstract: A semiconductor device in which the cell size is small and disturbance in reading operation is suppressed, and a method for manufacturing the semiconductor device. A first memory cell has a first memory transistor. A second memory cell has a second memory transistor. A control gate is shared by the first memory cell and the second memory cell. In plan view, the control gate is sandwiched between a first memory gate of the first memory transistor and a second memory gate of the second memory transistor.
    Type: Grant
    Filed: October 29, 2017
    Date of Patent: August 20, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiyuki Kawashima, Takashi Hashimoto
  • Semiconductor device with arrangement of semiconductor regions for improving breakdown voltages
    Patent number: 10388741
    Abstract: A first p type semiconductor region is provided between an n type drift region surrounding a drain region and an n type buried region, and a second p type semiconductor region is provided between the first p type semiconductor region and a p type well region surrounding a source region so as to overlap the first p type semiconductor region and the p type well region. Negative input breakdown voltage can be ensured by providing the first p type semiconductor region over the n type buried region. Further, potential difference between the source region and the first p type semiconductor region can be increased and the hole extraction can be performed quickly. Also, a path of hole current flowing via the second p type semiconductor region can be ensured by providing the second p type semiconductor region. Thus, the on-breakdown voltage can be improved.
    Type: Grant
    Filed: January 21, 2017
    Date of Patent: August 20, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takahiro Mori
  • Method and apparatus for minimizing voltage droop due to load step during energy conservation operation
    Patent number: 10389248
    Abstract: The present embodiments are directed to circuitry and techniques for operating a switching regulator, including in connection with transitions out of energy conservation modes during which a minimal amount of current is drawn from a power source such as a battery. According to certain aspects, embodiments of an energy conservation mode include provisions for maintaining high performance voltage regulation even in the face of a sudden increase in load requirements. These and other embodiments can further include various techniques for signaling an appropriate transition for exiting out of energy conservation mode and into a continuous conduction mode.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: August 20, 2019
    Assignee: RENESAS ELECTRONICS AMERICA INC.
    Inventors: Byongho Park, Edward Coleman, Chris Jurado, Shawn Evans, Noboru Kagemoto, Daniel Zheng
  • Semiconductor device and manufacturing method thereof
    Patent number: 10388779
    Abstract: A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 20, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto
  • Task processor
    Patent number: 10387191
    Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: August 20, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Naotaka Maruyama
  • Semiconductor device and manufacturing method thereof
    Patent number: 10386586
    Abstract: A Si photonics device includes: a first semiconductor chip; a second semiconductor chip having a laser diode and mounted on the first semiconductor chip; a third semiconductor chip taking in a laser beam emitted from the laser diode and mounted on the first semiconductor chip; and a resin layer disposed on the first semiconductor chip so as to face the second semiconductor chip. Further, the Si photonics device has: a bump electrode connecting the second semiconductor chip and an upper layer electrode pad provided on the resin layer of the first semiconductor chip; and a bump electrode connecting the first semiconductor chip and the third semiconductor chip, and the second semiconductor chip is mounted on the first semiconductor chip via the resin layer.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: August 20, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Iida, Yasutaka Nakashiba
  • Current output circuit
    Patent number: 10379693
    Abstract: A current output circuit includes a separation circuit that separates a digital pseudo sine wave into first and second digital pseudo half-waves, a first digital-to-analog (DA) converter that converts the first digital pseudo half-wave into a first analog half-wave signal, and a second DA converter that converts the second digital pseudo half-wave into a second analog half-wave signal. The pseudo sine wave is represented by a digital code having an n bit width, in which n is a natural number. The separation circuit includes a plurality of OR circuits that output a logical OR between a value of a most significant bit representing a code in the digital code and values of bits other than the most significant bit as the first pseudo half-wave.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 13, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kosuke Fuwa
  • Communication device, LSI, program, and communication system
    Patent number: 10382419
    Abstract: An object of the present invention is to prevent an attack from or via a communication device on an information apparatus in a communication system including the information apparatus, the communication device coupled to the information apparatus in the aftermarket, a server that authenticates the communication device, and a communication unit between the communication device and the server. A communication device includes a first interface that performs first communications with a server, a second interface that performs second communications with an information apparatus, and an information processing unit that performs an information process including a communication protocol process accompanied by the first and second communications.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: August 13, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Daisuke Oshida
  • Method of manufacturing semiconductor device
    Patent number: 10381318
    Abstract: The present invention: makes it possible to improve the reliability of a semiconductor device; and provides a method of manufacturing the semiconductor device comprising the steps of (a) providing a semiconductor wafer having a pad electrode, a first conductive layer comprised of copper, a photoresist film, and a second conductive layer comprised of gold, (b) forming a protective film comprised of iodine on the surface of the second conductive layer, (c) removing the photoresist film, (d) irradiating the protective film with argon ions and removing the protective film, and (e) bringing a part of a bonding wire into contact with the surface of the second conductive layer.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: August 13, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yuki Yagyu
  • Computer system
    Patent number: 10379931
    Abstract: A computer system includes a first bus, a second bus, and a third bus, a first bus bridge that is disposed between the first bus and the second bus, and detects a bus error on the second bus, a second bus bridge that is disposed between the second bus and the third bus, and detects a bus error on the third bus, a first device coupled to the second bus, a second device coupled to the third bus, an interrupt controller that notifies a bus error in accordance with the detection of the bus error, and a multi-thread processor. The multi-thread processor includes a schedule register that stores an execution order and data for a plurality of virtual CPUs, and a virtual CPU execution circuit that executes the virtual CPUs in accordance with the execution order.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: August 13, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hirotaka Motai, Yasuhiro Tawara, Koji Adachi, Hitoshi Suzuki
  • Manufacturing method of semiconductor device
    Patent number: 10381444
    Abstract: To improve the performance of a semiconductor device, there is provided with a manufacturing method of a semiconductor device including a step of removing an oxide film formed on the surface of a silicon carbide substrate including the inner wall of a trench, before forming the hydrogen annealing.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: August 13, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Youichi Yamamoto
  • Method of manufacturing semiconductor device and semiconductor device
    Patent number: 10381279
    Abstract: To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 13, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Akira Yajima
  • Magnetism measuring device
    Patent number: 10379069
    Abstract: A magnetism measuring device includes a light source unit, a diamond crystal and an image sensor. The light source unit irradiates the diamond crystal with an excitation light, and irradiates the image sensor with a fluorescent light generated by the diamond crystal. The diamond crystal includes a plurality of nitrogen-vacancy pairs. The image sensor detects an intensity of the fluorescent light, which is generated from the diamond crystal, by a plurality of pixels. The image sensor and the light source unit are disposed so as to be contained within a projection area of the diamond crystal.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 13, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yuji Hatano, Jun Ueno, Takenori Okitaka, Keiro Komatsu