Abstract: In an optical waveguide section of an SIS type having a configuration of stacking a second semiconductor layer over a first semiconductor layer with a dielectric layer interposed, the first semiconductor layer is electrically coupled to a first electrode at a first lead-out section where the second semiconductor layer is not stacked. Further, the second semiconductor layer is electrically coupled to a second electrode at a second lead-out section not overlapping with the first semiconductor layer. As a result, when a contact hole for forming the second electrode is formed by dry etching, the dielectric layer between the first semiconductor layer and the second semiconductor layer is not damaged or broken and hence short-circuit failure between the first semiconductor layer and the second semiconductor layer can be prevented. The reliability of the optical waveguide section therefore can be improved.

Abstract: A subject matter of this invention is that a manufacturing yield of a semiconductor device is improved. A resistance value between a pogo pin and a test pin is measured by bringing a plurality of pogo pins of a socket mounted over a test board included in an inspection device of a semiconductor device into contact with a plurality of solder balls, respectively, and bringing the test pin provided in the socket into contact with a first solder ball of a plurality of solder balls at a position different from a position where the pogo pin is brought into contact with the first solder ball. Thereby, a coupling failure between the pogo pin and the first solder ball is detected, so that a conductive state is inspected.

Abstract: A semiconductor device includes: an encoding processing unit that stores an encoded stream of an input data that is encoded based on the specified encoding control information; a buffer management unit that calculates the transmission buffer occupancy indicating the amount of data stored in a transmission buffer according to the generated data amount, and the reception buffer occupancy indicating the amount of data stored in a reception buffer, which is the destination of the encoded stream; and a control information specifying unit that, when the transmission buffer occupancy is equal to or less than a first threshold, specifies the encoding control information based on the reception buffer occupancy, and when the transmission buffer occupancy is greater than the first threshold, specifies the encoding control information to further reduce the generated data amount than in the case of equal to or less than the first threshold, to the encoding processing unit.

Abstract: The variation of the oscillation frequency of an oscillator can be suppressed even in the case where the amount of interference with the oscillator accompanied by an amplifying operation of a power amplifier and the polarity are not constant. An oscillator is configured to be capable of oscillating at an oscillation frequency in accordance with control signals Vcont and FREQ_CTRL. A phase locked loop allows the oscillator to output an oscillation signal Vout in synchronization with a reference signal RELCLK using the control signal Vcont. A power amplifier amplifies the electric power of the oscillation signal Vout. A variation detection unit detects a variation with respect to the time change of the control signal Vcont after an amplifying operation is started by the power amplifier causing 3interference with the oscillator.

Abstract: A metal wiring layer includes a plurality of hierarchical blocks each divided by a side that serves as a boundary. One of the hierarchical blocks is placed to extend along the outer periphery of the self hierarchical block, and includes: a shield ring wire formed by a single metal wire or by a plurality of metal wires; and a plurality of metal wires that are placed inside the shield ring wire and extend in a preferential direction determined in advance. The shield ring wire has a first section extending in the preferential direction and a second section extending in a non-preferential direction perpendicular to the preferential direction.

Abstract: An image processing device includes a luminance modulator operable to receive a video input signal and operable to calculate a video output signal to be supplied to a display panel, a peak value detector operable to calculate a peak value as a maximum luminance in a prescribed region of the video input signal, a histogram detector operable to calculate frequency distribution about a luminance value of the video input signal in the prescribed region, a peak Automatic contrast level (ACL) control gain calculation unit operable to calculate a peak ACL control gain with which luminance of each pixel of the video input signal is amplified, based on the ratio of the peak value to a maximum possible value of the video output signal, and a pattern-adaptive gamma characteristic calculation unit operable to calculate a luminance modulation gain.

Abstract: An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

Abstract: In an on-vehicle system, the gateway is duplexed, and a countermeasure table is included. The countermeasure table defines a failure phenomenon occurring in communication, an identification method for identifying a factor on whether the failure phenomenon is caused by a failure of the gateway or caused by a security attack on the gateway, and a corresponding countermeasure method. When it is detected that a failure phenomenon has occurred is communication through the gateway, the on-vehicle system determines a factor of the detected failure phenomenon based on the identification method defined in the countermeasure table, and makes countermeasures in accordance with the corresponding countermeasure method.

Abstract: A semiconductor device using an SOI (Silicon On Insulator) substrate, capable of preventing malfunction of MISFETs (Metal Insulator Semiconductor Field Effect Transistor) and thus improving the reliability of the semiconductor device. Moreover, the parasitic resistance of the MISFETs is reduced, and the performance of the semiconductor device is improved. An epitaxial layer formed on an SOI layer above an SOI substrate is formed to have a large width so as to cover the ends of the upper surface of an isolation region adjacent to the SOI layer. By virtue of this, contact plugs of which formation positions are misaligned are prevented from being connected to a semiconductor substrate below the SOI layer. Moreover, by forming the epitaxial layer at a large width, the ends of the SOI layer therebelow are prevented from being silicided. As a result, increase in the parasitic resistance of MISFETs is prevented.

Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.

Abstract: In a semiconductor device including a higher-breakdown-voltage MISFET, an improvement is achieved in the breakdown voltage of the MISFET, while preventing an increase in the area of the MISFET. A gate pattern including a gate electrode of the higher-breakdown-voltage MISFET is formed higher in level than a gate pattern including a gate electrode of a lower-breakdown-voltage MISFET. An n+-type semiconductor region included in each of source/drain regions of the higher-breakdown-voltage MISFET is formed deeper than an n+-type semiconductor region included in each of source/drain regions of the lower-breakdown-voltage MISFET.

Abstract: An apparatus that includes a first device connected to an inductor. The first device includes a first silicon carbide (SiC) junction gate field-effect transistor (JFET), a first SiC schottky barrier diode (SBD) connected to a gate and a drain of the first SiC JFET, and a first silicon (Si) transistor connected to transmit current to a source of the first SiC JFET. An inductor input terminal is connected to the drain of the first SiC JFET.

Abstract: To provide an abnormality detection system capable of reducing work load of an engineer. An algorithm storage unit stores therein a detection algorithm corresponding to identification information of a detection target. An abnormality detection unit detects an abnormality in a detection target signal obtained from a monitor signal of the detection target using a corresponding detection algorithm in the algorithm storage unit. A detection target identification unit determines whether the detection algorithm corresponding to the identification information of the detection target is stored in the algorithm storage unit, and issues a generation request when it is not stored therein. An algorithm generation unit generates the detection algorithm using a corresponding detection target signal according to the generation request.

Abstract: There are provided a highly reliable semiconductor device capable of suppressing occurrence of cracks as well as securing flatness and a manufacturing method therefor. The semiconductor device includes: a semiconductor substrate; an element region; and a non-element region. The non-element region includes: a top-layer metal wiring in a top layer of metal wirings formed in the non-element region; a flattening film covering an upper surface of the top-layer metal wiring; and a protecting film formed over the flattening film. A removed part where the protecting film is removed is formed in at least part of the non-element region.

Abstract: An abnormal rise of oscillation frequencies of PLL circuits in conventional semiconductor devices has been an inevitable problem. This semiconductor device includes a phase difference detection circuit, a loop filter, and a voltage controlled oscillator that outputs an output clock signal. The voltage controlled oscillator includes a voltage-current converter that generates a control current having a current value in accordance with the voltage level of a frequency control voltage, an oscillator that varies the frequency of the output clock signal in accordance with the current value of the control current, and a current limiter that limits the current flowing in the oscillator in accordance with a limiting voltage transmitted through a signal-flow path provided independently from the other circuits.

Abstract: A semiconductor device with a FINFET, which provides enhanced reliability. The semiconductor device includes a first N channel FET and a second N channel FET which are coupled in series between a wiring for output of a 2-input NAND circuit and a wiring for a second power potential. In plan view, a local wiring is disposed between a first N gate electrode of the first N channel FET and a second N gate electrode of the second N channel FET which extend in a second direction, and crosses a semiconductor layer extending in a first direction and extends in the second direction. The local wiring is coupled to a wiring for heat dissipation.

Abstract: An SCI can perform transmission only or reception only, however, it is necessary to reset the SCI when transmission and reception is switched to transmission only or to reception only. A semiconductor device includes an interface circuit which performs a sequential communication of transmit or receive according to a synchronous clock. The interface circuit includes a register to specify an operation enabled state which is at least one of a transmit state and a receive state, and a mode control circuit to change at least one mode of transmit or receive in the operation enabled state.

Abstract: Resistance of a gate electrode is reduced in a split gate MONOS memory configured by a fin FET. A memory gate electrode of a split gate MONOS memory is formed of a first polysilicon film, a metal film, and a second polysilicon film formed in order on a fin. A trench between fins adjacent to each other in a lateral direction of the fins is filled with a stacked film including the first polysilicon film, the metal film, and the second polysilicon instead of the first polysilicon film only.

Abstract: According to one embodiment, a semiconductor device 1 includes a temperature sensor module 10 that outputs a non-linear digital value with respect to temperature and a substantially linear sensor voltage value with respect to the temperature, a storage unit 30 that stores the temperature, the digital value, and the sensor voltage value, and a controller 40 that calculates a characteristic formula using the temperature, the digital value, and the sensor voltage value stored in the storage unit 30, in which the temperature, the digital value, and the sensor voltage value stored in the storage unit 30 include absolute temperature under measurement of absolute temperature, the digital value at the absolute temperature, and the sensor voltage value at the absolute temperature.

Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.