Abstract: A plurality of IO cells are arranged along an edge portion of a semiconductor chip. Some elements forming a reference voltage generation circuit are arranged in a first corner region of the semiconductor chip. Remaining elements forming the reference voltage generation circuit are arranged in a core region on an inner side of the edge portion of the semiconductor chip. Among a plurality of corner regions, the first corner region is located closest to the remaining elements.

Abstract: An interface circuit provided in a semiconductor device supplies an operation clock to an external memory device based on a clock signal (CK) and receives a data signal (DQ) and a strobe signal (DQS) from the external memory device. The interface circuit includes a delay circuit delaying the received strobe signal (DQS). The delay circuit includes a first adjustment circuit and a second adjustment circuit connected in series with the first adjustment circuit. The first adjustment circuit is capable of adjusting a delay amount of the strobe signal (DQS) in a plurality of steps in accordance with the set frequency of the clock signal (CK). The second adjustment circuit is capable of adjusting the delay amount of the strobe signal (DQS) with a higher precision than the first adjustment circuit.

Abstract: A load driving method includes bringing an output transistor disposed between a first power supply line and an output terminal connected to a load into a conduction state by a protection transistor provided between a gate of the output transistor and a second power supply line when a polarity of a power supply coupled between the first power supply line and the second power supply lines is reversed, and forming a conductive path between the second power supply line and a back gate of the protection transistor via a transistor by a back gate control circuit when the polarity of the power supply is normal, the back gate control circuit including the transistor, a gate of the transistor being coupled to the first power supply line directly via a connection node located in a connecting line that couples the first power supply line and the output transistor, the transistor being coupled between the second power supply line and the back gate of the protection transistor.

Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.

Abstract: In order to improve the characteristics of a semiconductor device including: a channel layer and a barrier layer formed above a substrate; and a gate electrode arranged over the barrier layer via a gate insulating film, the semiconductor device is configured as follows. A silicon nitride film is provided over the barrier layer between a source electrode and the gate electrode, and is also provided over the barrier layer between a drain electrode and the gate electrode GE. The surface potential of the barrier layer is reduced by the silicon nitride film, thereby allowing two-dimensional electron gas to be formed. Thus, by selectively forming two-dimensional electron gas only in a region where the silicon nitride film is formed, a normally-off operation can be performed even if a trench gate structure is not adopted.

Abstract: To provide an imaging device equipped with a photodiode, which is capable of enhancing both of a capacity and sensitivity. In an area of a P-type well in which a photodiode is formed, a P-type impurity region is formed from the surface of the P-type well to a predetermined depth. Further, an N-type impurity region is formed to extend to a deeper position. N-type impurity regions and P-type impurity regions respectively extending in a gate width direction from a lower part of the N-type impurity region to a deeper position so as to contact the N-type impurity region are alternately arranged in a plural form along a gate length direction in a form to contact each other.

Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.

Abstract: The reliability of a semiconductor device is improved. A semiconductor device in accordance with one embodiment has a plurality of stacked semiconductor chips. Further, a plurality of inter-chip connection members (conductive members) arranged between the semiconductor chips, and establishing an electrical connection between the semiconductor chips include a first inter-chip connection member (conductive member) for passing therethrough a current with a first frequency, and a plurality of second inter-chip connection members (conductive members) for passing therethrough a signal current with a second frequency higher than the first frequency. Further, in the second inter-chip connection members, at least some of the second inter-chip connection members arranged adjacent to each other are in contact with each other, and are separated from the first inter-chip connection member.

Abstract: The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and execute a task in accordance with the data in the processing register. The save circuit is provided with a plurality of save registers respectively associated with a plurality of tasks. In executing a predetermined system call, the execution control circuit notifies the task control circuit as such. The task control circuit switches between tasks for execution upon receipt of the system call signal, by saving, in the save register associated with a task being executed, the data in the processing register, selecting a task to be executed next, and loading data in the save register associated with the selected task into the processing register.

Abstract: In wire bonding in assembling of a semiconductor device, an Al wire is coupled to a lead section by a wedge which is a bonding tool, thereafter, the wedge is withdrawn from the top of the lead section and a cutter is lowered and the Al wire is cut off in this state. Lowering of the cutter is stopped at a point in time that a stopper which is lowered simultaneously with lowering of the cutter has truck against the lead section and cutting of the Al wire is terminated by stopping of lowering of the cutter.

Abstract: There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film.

Abstract: In an SOP1 having a semiconductor chip and another semiconductor chip, in wire coupling between the chips, a withstand voltage can be secured by setting an inter-wire distance between a wire in a first wire group that is closest to a second wire group and a wire in the second wire group that is closest to the first wire group to be larger than an inter-wire distance between any wires in the first wire group and the second wire group, which makes it possible to attain improvement of reliability of the SOP1.

Abstract: Switching loss is reduced by decreasing the switching frequency of a PFC power supply in light load condition, whereas the switching frequency is maintained high in heavy load operation. Efficiency in light load operation is thus improved without enlarging a boosting inductor and an output smoothing capacitor. A capacitor is provided in a triangular wave generating circuit and the triangular wave generating circuit outputs a triangular wave by charging and discharging this capacitor. Charging and discharging of the capacitor are controlled by an oscillation frequency control circuit output current which is input to a comparator.

Abstract: Reliability of a semiconductor device is improved, and use efficiency of a sputtering apparatus is increased. When depositing thin films over a main surface of a semiconductor wafer using a magnetron sputtering apparatus in which a collimator is installed in a space between the semiconductor wafer and a target installed in a chamber, a region inner than a peripheral part of the collimator is made thinner than the peripheral part. Thus, it becomes possible to suppress deterioration in uniformity of the thin film in a wafer plane, which may occur as the integrated usage of the target increases.

Abstract: The ringing of a switching waveform of a semiconductor device is restrained. For example, an interconnect (L5) is laid which functions as a source of a power transistor (Q3) and a cathode of a diode (D4), and further functioning as a drain of a power transistor (Q4) and an anode of a diode (D3). In other words, a power transistor and a diode coupled to this power transistor in series are formed in the same semiconductor chip; and further an interconnect functioning as a drain of the power transistor and an interconnect functioning as an anode of the diode are made common to each other. This structure makes it possible to decrease a parasite inductance between the power transistor and the diode coupled to each other in series.

Abstract: The present invention makes it possible to improve the reliability of a semiconductor device. In a manufacturing method of a semiconductor device according to an embodiment, when a resist pattern is formed over a cap insulating film comprising a silicon nitride film, the resist pattern is formed through the processes of coating, exposure, and development treatment of a chemical amplification type resist. Then the chemical amplification type resist is applied so as to directly touch the surface of the cap insulating film comprising the silicon nitride film and organic acid pretreatment is applied to the surface of the cap insulating film comprising the silicon nitride film before the coating of the chemical amplification type resist.

Abstract: A semiconductor device includes: a voltage generation unit that generates a first voltage having a first temperature characteristic; a constant voltage generation unit that generates a constant voltage; and an adjustment unit that generates a second voltage having a second temperature characteristic and a third voltage having a third temperature characteristic using the first voltage and the constant voltage. The constant voltage generation unit generates the constant voltage independently of the adjustment unit. One of the second and third temperature characteristics is an opposite characteristic to the first temperature characteristic. The device can also include a control unit that selects one of the second and third voltages in response to a predetermined setting value.

Abstract: An object is to provide a reliability-improved semiconductor device having a MONOS memory that rewrites data by injecting carriers into a charge storage portion. When a memory gate electrode having a small gate length is formed in order to overlap a carrier injection position in write operation with that in erase operation, each into an ONO film including a charge storage portion, the ONO film is formed in a recess of a main surface of a semiconductor substrate for securing a large channel length. In a step of manufacturing this structure, control gate electrodes are formed by stepwise processing of a polysilicon film by first and second etching and then, the recess is formed in the main surface of the semiconductor substrate on one side of the control gate electrode by second etching.

Abstract: A rectangular optical waveguide, an optical phase shifter and an optical modulator each formed of a semiconductor layer are formed on an insulating film constituting an SOI wafer, and then a rear insulating film formed on a rear surface of the SOI wafer is removed. Moreover, a plurality of trenches each having a first depth from an upper surface of the insulating film are formed at a position not overlapping with the rectangular optical waveguide, the optical phase shifter and the optical modulator when seen in a plan view in the insulating film. As a result, since an electric charge can be easily released from the SOI wafer even when the SOI wafer is later mounted on the electrostatic chuck included in the semiconductor manufacturing apparatus, the electric charge is less likely to be accumulated on the rear surface of the SOI wafer.

Abstract: A semiconductor device, includes a die pad that has a first main surface and a second main surface located on the opposite side of the first main surface; a lead arranged next to the die pad; a semiconductor chip that has a surface, a first electrode and a second electrode formed on the surface, and a reverse side located on the opposite side of the surface, and is mounted on a chip mounting area of the first main of the die pad; a first wire that electrically couples the first electrode of the semiconductor chip and the lead; a second wire that electrically couples the second electrode of the semiconductor chip and the die pad; and a sealed body that seals the semiconductor chip, the first wire, and the second wire.