Abstract: A deep trench which reaches a predetermined depth from one principal surface is formed in an element region of a semiconductor substrate. A TEOS oxide film and a polycrystalline silicon film are formed so as to fill the deep trench. In formation of a MOSFET and in formation of a protective insulating film on/over a surface of an element region by thermal oxidation, a silicon thermal oxide film grows, the TEOS oxide film contracts and the polycrystalline silicon film expands when oxidized and turning into a silicon oxide film, and thereby an embedded insulator is formed in the deep trench.

Abstract: A circuit (11) for controlling slew rate of a high-side switching element (6) in a load switch (5) is described. The circuit includes a variable current source (20) for setting a slew rate. The circuit also includes an amplifier (15) comprising a first input coupled to a fixed voltage source (19), a second input coupled to the variable current source and an output (18) for a drive signal. A feedback path (26) from an input terminal (13), connected or connectable to an output (14) of the switching element, to the second input of the amplifier, includes a series voltage-differentiating element, such as a capacitor (27).

Abstract: The detection of a fault of the address signal system in memory access is aimed at. A semiconductor device according to the present invention includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.

Abstract: A method and apparatus for implementing power modes in microcontrollers (MCUs) using power profiles. In one embodiment of the method, a central processing unit (CPU) of the MCU executes a first instruction for calling a subroutine stored in a memory of the MCU, wherein the first instruction comprises a first parameter to be passed to the subroutine. Thereafter the CPU writes a first value to a first special function register (SFR) of the MCU in response to executing the first instruction, wherein the first value is related to the first parameter. The MCU operates in a first power mode in response to the CPU writing the first value to the first SFR. The CPU also executes a second instruction for calling the subroutine, wherein the second instruction comprises a second parameter to be passed to the subroutine. In response the CPU writes a second value to a second SFR of the MCU in response to executing the second instruction, wherein the second value is related to the second parameter.

Abstract: The characteristics of a semiconductor device are enhanced. In a semiconductor device (MISFET) having a gate electrode GE formed on a nitride semiconductor layer CH via a gate insulating film GI, the gate insulating film GI is configured to have a first gate insulating film (oxide film of a first metal) GIa formed on the nitride semiconductor layer CH and a second gate insulating film (oxide film of a second metal) GIb. And, the second metal (e.g., Hf) has lower electronegativity than the first metal (e.g., Al). By thus making the electronegativity of the second metal lower than the electronegativity of the first metal, a threshold voltage (Vth) can be shifted in a positive direction. Moreover, the gate electrode GE is configured to have a first gate electrode (nitride film of a third metal) GEa formed on the second gate insulating film GIb and a second gate electrode (fourth metal) GEb.

Abstract: Provided is a high-speed and light-weighted authentication system that makes IP address filtering possible and does not impair real-time property even on a network including many and unspecific entities (communication devices). In a communication system that a plurality of communication devices are coupled together such that mutual communication is possible over the network, the communication devices communicate with a server under a secure environment, when authentication has been obtained from the server, random seeds of the same value and individual identifiers are issued to them, each communication device generates the IP address that includes a pseudorandom number and the identifier, and the communication devices establish communication between the communication devices that include the pseudorandom numbers that are mutually the same in their IP addresses.

Abstract: A method and apparatus for microcontroller (MCU) memory relocation. The MCU includes a central processing unit (CPU) and memory, but lacks a memory management unit (MMU). In one embodiment of the method, a first program is selected for execution by the CPU. The first program is one of a plurality of programs stored in the memory of the MCU. Each of the programs includes position dependent instructions. The programs are compiled from source code written in position dependent code.

Abstract: A semiconductor storage device includes, a memory array, a plurality of memory cells provided in rows and columns, and a control circuit for controlling the memory array, each of the memory cells being a static-type memory cell comprising driving transistors, transfer transistors, and load elements.

Abstract: The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.

Abstract: To provide a signal generation circuit having a short settling time of an output voltage. In a PTAT signal generation circuit, a trimming circuit is coupled between the cathodes of 0-th to K-th diodes and a line of a ground voltage, the anode of the 0-th diode is coupled to a first node, the anodes of the first to the K-th diodes are coupled to a second node via a resistive element, the first node and the second node are set to the same voltage, a first current flowing through the 0-th diode and a second current flowing through the first to the K-th diodes are set to have the same value, and a third current flowing through the trimming circuit is set to have the value 2 times that of each of the first current and the second current.

Abstract: An electronic device has a control board having a plurality of wiring layers, a metal-made housing supporting the control board, and a fixing screw for fixing the control board to the housing through a washer. The control board includes a through hole penetrating from a third surface to a fourth surface, a through electrode formed inside the through hole, and a power system GND pattern formed on any wiring layer of the wiring layers. The power system GND pattern and the housing are electrically coupled through the through electrode, the washer, and the fixing screw.

Abstract: A semiconductor device includes an N number of sub-blocks each of including a memory cell array, a setting register specifying number of entry data for pre-searching, of first to N-th entry data divided and correspond respectively to the sub-blocks, and a search data changing unit changing a data arrangement order for search data input based on a value of the register. A sub-block for pre-searching searches for entry data matching with data for pre-searching in accordance with the arrangement order changed by the changing unit, in response to an instruction, and outputs a search result representing matching or non-matching. A sub-block for post-searching searches for entry data matching with data for post-searching other than the data for pre-searching, of entry data stored in association with each row of the array, based on a search result of the sub-block for pre-searching, and outputs a search result representing matching or non-matching.

Abstract: The semiconductor device according to one embodiment includes a power transistor and a sense transistor connected in parallel with each other, a first operational amplifier having a non-inverting input terminal connected to an emitter of the sense transistor and an inverting input terminal connected to an emitter of the power transistor, a resistor element having one end connected to the emitter of the sense transistor and another end connected to a first node, and an adjustment transistor placed between the first node and a low-voltage power supply. The first operational amplifier adjusts a current flowing through the adjustment transistor so that an emitter voltage of the power transistor and an emitter voltage of the sense transistor are substantially the same.

Abstract: The consumption current of a TCAM device is reduced. A semiconductor device includes multiple sub-arrays each including a TCAM cell array. Each sub-array searches the corresponding part of the input search data. Each sub-array outputs the search result indicative of a match for every entry without searching, when the corresponding first control signal is activated.

Abstract: There is a need to improve estimation accuracy of a failure estimation method or its failure estimation apparatus that performs failure estimation on a targeted instrument based on history information about several instruments mounted with the same type of semiconductor device as an instrument targeted at failure estimation. A failure estimation apparatus that includes a history information database storing history information about a plurality of instruments mounted with the same type of semiconductor device and performs failure estimation on a targeted instrument mounted with a semiconductor device whose type equals the type, wherein the history information contains operation information and failure information; wherein the operation information indicates a chronological operating state of the semiconductor device mounted on the instruments; wherein the failure information indicates a failure cause of a failed instrument; and wherein the operating state is categorized into a plurality of classifications.

Abstract: Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core and the second CPU core respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnosed result.

Abstract: A rate determination apparatus 1 includes a reception unit 2 configured to receive a transmission frame modulated by an FSK modulation scheme, a symbol rate detection unit 3 configured to detect a symbol rate based on a period of a preamble portion in the received transmission frame, a multilevel symbol detection unit 4 configured to detect a multilevel-modulated multilevel symbol based on a frequency deviation in the received transmission frame, and a bit rate determination unit 5 configured to determine a bit rate based on the detected symbol rate and the detected multilevel symbol. Then, the bit rate can be determined during communication.

Abstract: The present invention provides a signal processor that improves a resolution of a phase detection without increasing a clock frequency of a controller or decreasing a frequency of an excitation signal. A signal processor 10 includes a comparator 11 that compares a signal obtained by phase modulating a carrier frequency at a rotor rotation angle of a resolver with a dither signal.

Abstract: A storage device includes a data memory unit and a status memory unit. The data memory unit includes a pair of flash memory cells to be read by a complementary read mode, and 1-bit data is stored therein by the pair of flash memory cells. The status memory unit includes a flash memory cell to be read by a reference read mode, and a status flag is stored therein by the flash memory cell.

Abstract: To improve current detection performance of a sense IGBT particularly in a low current region in a semiconductor device equipped with a main IGBT and the sense IGBT used for current detection of the main IGBT. At a peripheral portion located at an outermost periphery of an active region surrounded by a dummy region within a sense IGBT cell, an n+-type semiconductor region is formed over an upper surface of a well of a floating state adjacent to a trench gate electrode embedded into a trench at an upper surface of a semiconductor substrate and applied with a gate voltage.