Abstract: An attribute group storage unit acquires and holds attribute groups set to respective data blocks. A scenario determination unit determines respective transfer systems of the respective blocks between a memory of the lowest hierarchy and a memory of another hierarchy based on those attribute groups and a configuration of an arithmetic unit which is the parallel processor, and controls the transfer of the respective data blocks according to the determined transfer systems, and the parallel arithmetic operation corresponding to the transfer. Each of the attribute groups is necessary to determine the transfer systems, and includes one or more attributes not depending on the configuration of the parallel processor. The attribute groups of the write blocks are set assuming that each of the write blocks has already been located in the memory of another hierarchy, and is transferred to the memory of the lowest hierarchy.

Abstract: For example, a semiconductor device has a lead connected to a second portion of a chip mounting part on which a semiconductor chip to be a heat source is mounted and a lead connected to a third portion of the chip mounting part on which the semiconductor chip to be the heat source is mounted. Further, each of the leads has a protruding portion protruding from a sealing member. In this manner, it is possible to enhance a heat dissipation characteristic of the semiconductor device.

Abstract: A semiconductor device includes a plurality of gate electrodes, and a plurality of stripe contacts, each formed alternately with each of the gate electrodes along a length direction of the gate electrodes. A conductive transistor with a reference potential applied to one of the stripe contacts forming one of a source and a drain is formed. One of the gate electrodes adjacent to one of the stripe contacts forming the other of the source and the drain is used as a first dummy gate electrode. The semiconductor device further includes a metal extending over the first dummy gate electrode to electrically connect together the stripe contacts formed on opposing sides of the first dummy gate electrode, and a pad connected to one of the stripe contacts formed on opposing sides of the first dummy gate electrode, which is provided across the first dummy gate electrode from the conductive transistor.

Abstract: An object of the present invention is to reduce capacitance of a charge accumulation part (floating diffusion) of each pixel unit. In an imaging device, in addition to a plurality of first switching transistors for coupling a plurality of coupling wires extending in the column direction, a second switching transistor is provided between each of the coupling wires and a floating diffusion in each pixel unit. Preferably, the gate of the first switching transistor and the gate of the second switching transistor are electrically coupled to each other.

Abstract: Disclosed as one aspect is a semiconductor device including a transmission/reception interface that is used for transmission and reception of data, a processing unit that processes the data, a monitoring unit that monitors received data and detects a specific frame allowed to be transmitted regardless of a state of a circuit to transmit/receive the data, and a power management unit that controls power consumption of a circuit including the processing unit.

Abstract: The present invention provides a solid-state imaging device conforming to different data transmission modes. A driver in a CMOS sensor includes a single-end driver which is provided in correspondence with two output terminals, activated in a parallel transmission mode, and outputs a corresponding data signal as a single-end signal to a corresponding output terminal; a serializer which is activated in a serial transmission mode and outputs a plurality of data signals which are supplied in parallel, serially one by one, and a differential driver which is activated in the serial transmission mode and outputs each of data signals output from the serializer as a differential signal to the output terminals.

Abstract: A sensor device includes a printed circuit board, a power line, a first semiconductor device, and a second semiconductor device. The first semiconductor device includes a first inductor, and the second semiconductor device includes a second inductor. Each inductor is formed using an interconnect layer. The power line extends between the two inductors without overlapping the first and second inductor, when viewed from a direction perpendicular to a main surface of the printed circuit board.

Abstract: The present invention provides a technique for achieving higher picture quality of a captured image by reducing noise which occurs at the time of resetting in a solid-state image sensing device and the like. A pixel array in a solid-state image sensing device includes a plurality of pixels and includes an OB pixel region and an effective pixel region. The solid-state image sensing device has a signal processing unit outputting a pixel signal of each of the pixels in the effective pixel region on the basis of the signal level of a signal output from each of the pixels. The solid-state image sensing device obtains a signal without applying a reset signal to each of the pixels in the OB pixel region, obtains the difference between the signal and a signal of a pixel in the effective pixel region, and outputs an image signal.

Abstract: An imaging device is provided which can secure the dynamic range of a COMS imaging sensor, by storing a charge overflowing from a floating diffusion in a storage capacitance element and suppressing the increase of a pixel area which occurs if the storage capacitance element is formed by a MOS capacitor. The imaging device includes plural pixel circuits arranged in the row direction and the column direction, and plural storage capacitance lines arranged in the row direction and extending in the column direction. Each of the storage capacitance lines is coupled to the pixel circuits arranged in the same column. The pixel circuit includes a first photoelectric conversion element which stores a charge generated by being subjected to light, a floating diffusion to which the charge stored in the first photoelectric conversion element is transferred, and a first switching transistor coupling the floating diffusion and the storage capacitance line.

Abstract: A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.

Abstract: A data processing apparatus includes an instruction execution section, a protection control information storage section that stores protection control information that includes first protection information, and second protection information that is independent of the first protection information, an instruction protection information storage section that stores instruction protection information for specifying a partial address space of an instruction address space in which to store instructions that are executable by the instruction execution section, a data protection information storage section that stores data protection information for specifying partial address spaces of a data address space in which to store operands to be usable by the instruction execution section, and a protection violation determination section which, when the first protection information includes a first value, makes a determination as to whether to permit the instruction execution section to access the instruction address space a

Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.

Abstract: The reliability of a semiconductor device is improved. In a manufacturing method, a film to be processed is formed over a circular semiconductor substrate, and a resist layer whose surface has a water-repellent property is formed thereover. Subsequently, the water-repellent property of the resist layer in the outer peripheral region of the circular semiconductor substrate is lowered by selectively performing first wafer edge exposure on the outer peripheral region of the semiconductor substrate, and then liquid immersion exposure is performed on the resist layer. Subsequently, second wafer edge exposure is performed on the outer peripheral region of the circular semiconductor substrate, and then the resist layer, on which the first wafer edge exposure, the liquid immersion exposure, and the second wafer edge exposure have been performed, is developed, so that the film to be processed is etched by using the developed resist layer.

Abstract: To enable a semiconductor device excellent in usability to be provided. A semiconductor device has a main surface surrounded by a plurality of sides, a semiconductor chip having a plurality of electrode pads arranged over the main surface, and a plurality of leads coupled to the electrode pads by way of wires respectively. The electrode pads include a plurality of first electrode pads supplied with a plurality of bits temporally in parallel. The first electrode pads include second and third electrode pads. A fourth electrode pad different from the first electrode pads is arranged between the second and third electrode pads.

Abstract: A portion-to-be-melted of a fuse is surrounded by plates, so that heat to be generated in a meltdown portion of the fuse under current supply can be confined or accumulated in the vicinity of the meltdown portion of the fuse. This makes it possible to facilitate meltdown of the fuse. The meltdown portion of the fuse in a folded form, rather than in a single here a fuse composed of a straight-line form, is more successful in readily concentrating the heat generated in the fuse under current supply into the meltdown portion, and in further facilitating the meltdown of the fuse.

Abstract: When a state of a radio communication device corresponds to a predetermined state, a communication control unit operates in the first mode to communicate according to the BLE standard, while when the radio communication device does not receive connect request packets, the communication control unit operates in the second mode to communicate. A rewrite switching unit switches to a rewritable state when the communication control unit operates in the first mode and to a rewriting prohibited state when the communication control unit operates in the second mode. The first mode is a mode for updating. In the first mode, the communication control unit transmits a notification for limiting the communication to the updating in an establishment process of the communication. The second mode is a mode for performing processing other than the updating. In the second mode, the communication control unit does not transmit the notification.

Abstract: An entry including multiple bits of unit cells each storing data bit is coupled to a match line. The match line is supplied with a charging current having a restricted current value smaller than a match line current flowing in a one-bit miss state in one entry, but larger than a match line current flowing in an all-bit match state in one entry. A precharge voltage level of a match line is restricted to a voltage level of half a power supply voltage or smaller. Power consumption in a search cycle of a content addressable memory can be reduced, and a search operation speed can be increased.

Abstract: A driver IC includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense MOS that is arranged between floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area. A fault detection circuit that detects presence of a fault when a voltage of the first sense node is higher than a decision voltage that has been deteLutined in advance in a period of time that a low side driver is driving a low side transistor into an ON state is formed in the first area.

Abstract: A host-side control unit 120 receives a terminal-device-side notification value INFD indicating a second voltage V2 that is a voltage at a reference point P2 on a terminal-device-side power supply line 134 from a terminal device 130, calculates a first resistance value R1 indicating a resistance from a power supply unit 112 to the reference point P2 based on the terminal-device-side notification value INFD, a first voltage V1 output by the power supply unit 112, and a first current A1 measured by a first current measurement unit 116, and supplies the calculated first resistance value R1 to the power supply unit 112. The power supply unit 112 adjusts the first voltage V1 according to the first resistance value R1 and the first current value A1 measured by the first current measurement unit 116 at that moment so that the second voltage V2 falls within a predetermined first reference range.

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.