Abstract: A performance of a semiconductor device including an RC-IGBT is improved. An AlNiSi layer (a layer containing aluminum (Al), nickel (Ni), and silicon (Si)) is formed between a back surface of a semiconductor substrate and a back surface electrode. Thus, a favorable ohmic junction can be obtained between the back surface electrode and an N+-type layer constituting a cathode region in an embedded diode, and a favorable ohmic junction can be obtained between the back surface electrode and a P-type layer constituting a collector region in an IGBT. The AlNiSi layer contains 10 at % or more of each of the aluminum (Al), the nickel (Ni), and the silicon (Si).

Abstract: An object of the present invention is to shorten the switching delay time of a semiconductor device. Transistor units are provided between a source bus line and a drain bus line that are provided apart from each other in a first direction, and a plurality of gate electrodes that extends in the first direction and is provided apart from each other in a second direction orthogonal to the first direction is provided in the transistor units. One ends of the gate electrodes on the source bus line side are coupled by a gate connection line extending in the second direction, and a gate bus line electrically coupled to the gate connection line is provided above the gate connection line. The gate electrodes and the gate connection line are formed using a wiring layer of the first layer, the source bus line and the drain bus line are formed using a wiring layer of the second layer, and the gate bus line is formed using a wiring layer of the third layer.

Abstract: An illegal address access blocking circuit includes a first register and a second register to set upper and lower limit values of an address range within which access to an external device is allowed. A first comparator compares a first value and the upper limit value, and outputs a high level signal when the first value is larger than the upper limit value. A second comparator compares the first value and the lower limit value, and outputs a low level signal. A first and logic circuit holds a logic sum of the high and low level signals, and outputs the logic sum as a third output, and a second logic circuit compares a fourth value inputted to a first request control line and the third output, and outputs a result of the comparison to a second request control line.

Abstract: In an equal width active cell IE type IGBT, a wide active cell IE type IGBT, and the like, an active cell region is equal in trench width to an inactive cell region, or the trench width of the inactive cell region is narrower. Accordingly, it is relatively easy to ensure the breakdown voltage. However, with such a structure, an attempt to enhance the IE effect entails problems such as further complication of the structure. The present invention provides a narrow active cell IE type IGBT having an active cell two-dimensional thinned-out structure, and not having a substrate trench for contact.

Abstract: In order to provide a semiconductor integrated circuit capable of predicting its own lifetime (wear out failure) due to the aged deterioration and notifying a warning, it includes a processor, a temperature sensor, a non-volatile memory, and a comparator formed on the same semiconductor substrate. The comparator compares a temperature measured by the temperature sensor with a predetermined temperature threshold, and the non-volatile memory accumulatively holds the information (cumulative time) about a period having the temperature exceeding the temperature threshold. The semiconductor integrated circuit notifies the outward of a warning when the cumulative time having the temperature exceeding the temperature threshold exceeds a predetermined high temperature time threshold.

Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.

Abstract: A radio frequency integrated circuit includes an amplification circuit for outputting a radio frequency signal to an antenna, a balun including a first terminal, a second terminal, a third terminal, and a fourth terminal, and a variable capacitance circuit including a fifth terminal and a sixth terminal. The first terminal and the second terminal of the balun receive output signals of the amplification circuit. The third terminal and the fourth terminal of the balun are connected to the fifth terminal and the sixth terminal of the variable capacitance circuit, respectively, and the fifth terminal is connected to a radio frequency output terminal. The variable capacitance circuit includes a plurality of capacity cells that are connected in parallel between two output terminals.

Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.

Abstract: The present invention prevents unauthorized functions from being installed to a predetermined storage unit in the background through a communication function that is being used for authorized communication operations and further prevents confidential information from being read out and stolen from the predetermined storage unit. A semiconductor device adopts an exclusive control unit that exclusively controls communication performed by a communication unit capable of communicating with the outside and access to a predetermined storage unit. For example, the communication status of the communication unit is determined based on whether a communication clock is active or inactive, and the exclusive control is exercised based on the determination result.

Abstract: A semiconductor device (1) according to the present invention includes a circuit to be tested (2) having a scan chain, and a first test control device (3) and a second test control device (4) that perform a scan test of the circuit to be tested by using the scan chain. The second test control device (4) performs a second scan test of the circuit to be tested (2), the circuit to be tested (2) gives the first test control device (3) an instruction to perform a first scan test after the second scan test is performed, and the first test control device (3) performs a first scan test of the circuit to be tested (2) in response to an instruction from the circuit to be tested (2).

Abstract: A semiconductor storage device having a plurality of low power consumption modes is provided. The semiconductor storage device includes a plurality of memory modules where a plurality of low power consumption modes can be set and cancelled based on a first and a second control signals. At least a part of memory modules of the plurality of memory modules have a propagation path that propagates an inputted first control signal to a post stage memory module. The second control signal is inputted into each of the plurality of memory modules in parallel. Setting and cancelling of the first low power consumption mode of each memory module are performed based on a combination of the first control signal that is propagated through the propagation path and the second control signal.

Abstract: A wireless communication apparatus includes a communication controller and an identification information setup portion. The communication controller establishes first communication, namely, communication with a first wireless communication apparatus having identification information already set and receives first information, namely, information to settle the identification information to be set, from the first wireless communication apparatus. The identification information setup portion sets the identification information for the wireless communication apparatus based on the first information.

Abstract: An exposure apparatus includes a polarizing member polarizing illumination light, and a filter having at least one opening. The polarizing member includes a first polarizing unit and a second polarizing unit arranged so as to surround the first polarizing unit. The second polarizing unit is configured so as to polarize the illumination light entering the second polarizing unit in the circumferential direction along the outer circumference of the first polarizing unit. At least a portion of the first polarizing unit is configured to polarize the illumination light in the direction orthogonal to the polarization direction in a part of the second polarizing unit located on the side opposite to the central part of the first polarizing unit. The openings are arranged in the filter so that the illumination light at the post stage of the filter and the polarizing member includes the illumination light polarized by the first and second polarizing units.

Abstract: An SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer is provided. A first region is one for forming a low breakdown voltage MISFET in the semiconductor layer, and a second region, in which the insulating layer and the semiconductor layer have been removed, is one for forming a high breakdown voltage MISFET. After an n-type semiconductor region is formed in the second region and an n-type extension region is formed in the first region, a first heat treatment is performed on the semiconductor substrate. Thereafter, a diffusion layer is formed in each of the first and second regions, and then a second heat treatment is performed on the semiconductor substrate. Herein, the time for which the first heat treatment is performed is longer than the time for which the second heat treatment is performed.

Abstract: The disclosed invention improves the transfer efficiency of a bus transfer device. A semiconductor device includes a bus transfer device including a read data transfer path which can transfer read data having an n-bit width at a maximum. If first read data and second read data corresponding respectively to a first transaction and a second transaction have a total bit width of n bits or less, the bus transfer device can simultaneously transfer data obtained by unifying the first read data and the second read data, first transaction identification information, and second transaction identification information through the read data transfer path.

Abstract: In a communication system in which a relay apparatus, a terminal apparatus, and other apparatuses, which can communicate with an authentication apparatus, are coupled through a communication path, the relay apparatus, and the terminal apparatus have unique authentication information, respectively. The relay apparatus transmits its own authentication information and authentication information collected from the terminal apparatus to the authentication apparatus. The authentication apparatus determines whether the relay apparatus and the terminal apparatus are authentic apparatuses based on the received authentication information. The relay apparatus shuts down communication between itself and an apparatus determined to be unauthentic based on a result of the determination, and transmits communication control information to shut down communication with the apparatus determined to be unauthentic to the terminal apparatus.

Abstract: A semiconductor device which reduces power consumption. In the semiconductor device, semiconductor chips are stacked over a base chip. The stacked chips include n through-silicon vias as a first group and m through-silicon vias as a second group. In each of the first and second groups, the through-silicon vias are coupled by a shift circular method, in which the 1st to (n?1)th ((m?1)th) through-silicon vias of a lower chip are coupled with the 2nd to n-th (m-th) through-silicon vias of an upper chip respectively and the n-th (m-th) through-silicon via of the lower chip is coupled with the 1st through-silicon via of the upper chip. n and m have only one common divisor. Activation of the stacked semiconductor chips is controlled by combination of a first selection signal transmitted through through-silicon vias of the first group and a second selection signal transmitted through through-silicon vias of the second group.

Abstract: A semiconductor device is provided where it is possible to access and test a memory chip by a simple method. The semiconductor device that mounts a plurality of chips in a common package includes a logic chip having a predetermined function and a memory chip that is coupled with the logic chip and stores data. The memory chip includes a memory chip testing circuit that performs an operation test of the memory chip and a serial bus interface circuit for transmitting and receiving data between the memory chip testing circuit and a serial bus provided outside the package.

Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

Abstract: An electronic device includes a first substrate, a wiring substrate (second substrate) disposed over the first substrate, and an enclosure (case) in which the first substrate and the wiring substrate are accommodated and that has a first side and a second side. A driver component (semiconductor component) is mounted on the wiring substrate. A gate electrode of a first semiconductor component is electrically connected to the driver component via a lead disposed on a side of the first side and a wiring disposed between the driver component and the first side. A gate electrode of a second semiconductor component is electrically connected to the driver component via a lead disposed on a side of the second side and a wiring disposed between the driver component and the second side.