Patents Assigned to RENESAS
  • Patent number: 9576921
    Abstract: To improve an integration degree of a semiconductor device. The semiconductor device includes a plurality of wiring layers formed on the semiconductor substrate, a pad electrode formed on an uppermost wiring layer among the plurality of wiring layers, a base insulating film having a pad opening above the pad electrode, and a rewiring electrically connected to the pad electrode and extending over the base insulating film. Further, the semiconductor device includes a protective film covering an upper surface of the rewiring and having an external pad opening exposing part of the upper surface of the rewiring, an external pad electrode electrically connected to the rewiring through the external pad opening and extending over the protective film, and a wire connected to the external pad electrode. Part of the external pad electrode is located in a region outside the rewiring.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: February 21, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Akira Yajima, Seiji Muranaka
  • Patent number: 9569261
    Abstract: The scheduler performs thread scheduling of repeating processings of specifying each hardware thread included in a first group among the multiple hardware threads for the number of times set up in advance for the hardware thread, and of specifying any one of the hardware threads in a second group for the number of times set up in advance for the second group that includes other hardware threads. Moreover, when the hardware thread in the first group specified by the thread scheduling is nondispatchable, the scheduler performs rescheduling of respecifying the hardware thread in the second group instead of the hardware thread in the first group.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: February 14, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Junichi Sato, Koji Adachi, Yousuke Nakamura
  • Patent number: 9570610
    Abstract: To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: February 14, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koichi Toba, Hiraku Chakihara, Yoshiyuki Kawashima, Kentaro Saito, Takashi Hashimoto
  • Patent number: 9570602
    Abstract: The present invention makes it possible to improve the accuracy of wet etching and miniaturize a semiconductor device in the case of specifying an active region of a vertical type power MOSFET formed over an SiC substrate by opening an insulating film over the substrate by the wet etching. After a silicon oxide film having a small film thickness and a polysilicon film having a film thickness larger than the silicon oxide film are formed in sequence over an epitaxial layer, the polysilicon film is opened by a dry etching method, successively the silicon oxide film is opened by a wet etching method, and thereby the upper surface of the epitaxial layer in an active region is exposed.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: February 14, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koichi Arai, Masaki Hama, Yasuaki Kagotoshi, Kenichi Hisada
  • Patent number: 9564388
    Abstract: A semiconductor device includes a base member and a first semiconductor chip mounted over the base member. The first semiconductor chip including a first circuit, a second circuit, and a third circuit arranged between the first circuit and the second circuit and a plurality of pads. The first, second and third circuits are arranged along a first side of the first semiconductor chip. In plan view, the pads are located outside of the circuits and include a plurality of first pads arranged at a first pitch, and a plurality of second pads arranged at the first pitch. A distance between a first pad group comprised of the first pads and a second pad group comprised of the second pads is larger than the first pitch. Further, in a plan view, a part of the third circuit is located between the first pad group and the second pad group.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: February 7, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masato Numazaki
  • Patent number: 9564486
    Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: February 7, 2017
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC., RENESAS ELECTRONICS CORPORATION
    Inventors: Murat Kerem Akarvardar, Steven John Bentley, Kangguo Cheng, Bruce B. Doris, Jody Fronheiser, Ajey Poovannummoottil Jacob, Ali Khakifirooz, Toshiharu Nagumo
  • Patent number: 9564426
    Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: February 7, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tohru Kawai, Yasutaka Nakashiba, Yutaka Akiyama
  • Patent number: 9564805
    Abstract: A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: February 7, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinya Sano, Masashi Horiguchi, Takahiro Miki, Mitsuru Hiraki
  • Publication number: 20170032760
    Abstract: An operational amplifier circuit includes: a first differential amplifier section containing a P-type differential pair of P-type transistors; a second differential amplifier section containing an N-type differential pair of N-type transistors; an intermediate stage connected with outputs of the first and second differential amplifier sections and containing a first current mirror circuit of P-type transistors, and a second current mirror circuit of N-type transistors; and an output stage configured to amplify an output of the intermediate stage in power. The first differential amplifier section includes a first current source and a first capacitance between sources of the P-type transistors of the P-type differential pair and a positive side power supply voltage. The second differential amplifier section includes a second current source and a second capacitance between sources of the N-type transistors of the N-type differential pair and a negative side power supply voltage.
    Type: Application
    Filed: October 12, 2016
    Publication date: February 2, 2017
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Kenji SHIMOMAKI
  • Patent number: 9559050
    Abstract: A method for manufacturing a semiconductor device includes forming a first conductor pattern and a second conductor pattern running side by side with each other, including forming a first portion of the first conductor pattern and a second portion of the second conductor pattern by patterning using a first mask, and forming a second portion of the first conductor pattern and a first portion of the second conductor pattern by patterning using a second mask. A first inter-conductor capacity is formed by the first portion of the first conductor pattern and the first portion of the second conductor pattern. A second inter-conductor capacity is formed by the second portion of the first conductor pattern and the second portion of the second conductor pattern.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tetsuya Watanabe
  • Patent number: 9558824
    Abstract: To improve information retention resistance of a resistance change memory which requires high information retention resistance. On the assumption that a special data storage memory and a general-purpose data storage memory are distinguished from each other, a forming operation small in resistance rise rate is used for an information writing operation of the special data storage memory. A switching operation is used for information writing of the general-purpose data storage memory. That is, the special data storage memory is configured so as to store information while adapting an initial resistance state to “0” whereas adapting a low resistance state to “1”. On the other hand, the general-purpose data storage memory is configured so as to store information while adapting a high resistance state to “0” whereas adapting a low resistance state to “1”.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Ueki, Takashi Hase, Yoshihiro Hayashi
  • Patent number: 9559183
    Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Patent number: 9560300
    Abstract: There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroto Utsunomiya, Katsumi Dosaka, Hiroshi Kato, Fukashi Morishita, Fumiyasu Sasaki
  • Patent number: 9558151
    Abstract: Disclosed is a data processing device capable of efficiently performing an arithmetic process on variable-length data and an arithmetic process on fixed-length data. The data processing device includes first PEs of SIMD type, SRAMs provided respectively for the first PEs, and second PEs. The first PEs each perform an arithmetic operation on data stored in a corresponding one of the SRAMs. The second PEs each perform an arithmetic operation on data stored in corresponding ones of the SRAMs. Therefore, the SRAMs can be shared so as to efficiently perform the arithmetic process on variable-length data and the arithmetic process on fixed-length data.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kan Murata, Hideyuki Noda, Masaru Haraguchi
  • Patent number: 9557790
    Abstract: In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Yamaki
  • Patent number: 9558832
    Abstract: To maintain constant an output voltage of a boosted voltage circuit even when a program current of a nonvolatile memory increases; in a boosted voltage circuit provided in a semiconductor device, an output voltage of a charge pump is detected by a voltage dividing circuit, and on-off control is performed on an oscillation circuit for driving the charge pump so that the detected output voltage becomes constant. Further, an output current of the charge pump is detected, and a control current according to a magnitude of the detected output current is generated. The control current is fed into or drawn from a coupling node between a plurality of series-coupled resistance elements configuring the voltage dividing circuit.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuaki Katou
  • Patent number: 9560762
    Abstract: A semiconductor device includes a semiconductor chip, a plurality of external terminals, and a board. The board includes a first main surface in which a plurality of first electrodes electrically connected to the semiconductor chip are formed, a second main surface in which a plurality of second electrodes electrically connected to the plurality of external terminals are formed, and a plurality of interconnect layers, provided between the first main surface and the second main surface, for forming a plurality of signal paths that electrically connect the first electrode and the second electrode corresponding thereto. The interconnect layer includes a plurality of metal members which are dispersedly disposed at a distance shorter than an electromagnetic wavelength equivalent to a signal band of a signal supplied to the signal path, in the vicinity of a portion in which a structure of an interconnect for forming the signal path is changed.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Ryuichi Oikawa
  • Patent number: 9559716
    Abstract: A processing speed can be improved while the accuracy of AD conversion is enhanced. An AD converter includes: a higher-order DAC that samples an analog input signal and performs DA conversion corresponding to higher-order bits of a digital output signal; an extension DAC that performs DA conversion to positive and negative polarities on an extension bit for expanding bits of the higher-order DAC; a lower-order DAC that performs DA conversion corresponding to lower-order bits of the digital output signal; a comparator that compares a comparison reference voltage with output voltages of the higher-order DAC, the extension DAC, and the lower-order DAC; and a successive approximation logic that controls successive approximation performed by the higher-order DAC, the extension DAC, and the lower-order DAC based on a comparison result of the comparator and generates the digital output signal.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuo Matsui, Hiroto Suzuki, Masaki Fujiwara, Tetsuro Matsuno
  • Patent number: 9558806
    Abstract: The number of terminals included in a semiconductor device which is included in an electronic device is reduced. The electronic device includes: a first semiconductor device having first and second input terminals; a second semiconductor device having a first output terminal and a first driver circuit to drive the first output terminal; and a wiring substrate over which the first and second semiconductor devices are mounted. The first and second input terminals are commonly coupled to the first output terminal via a first line formed on the wiring substrate. A composite resistance value of first and second termination resistors coupled to the first and second input terminals, respectively, is equivalent to a drive impedance of the first driver circuit.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Motoo Suwa, Takafumi Betsui, Masato Suzuki
  • Patent number: 9554137
    Abstract: To improve an image recognition rate by quickly changing a parameter in a proper manner without being affected by a transmission delay of an image encoding stream in an image receiving device that recognizes a decoded image obtained by decoding the received image encoding stream. The image receiving device includes a data receiving unit, a parameter changing unit, a decoding unit, and an image recognition unit. The data receiving unit receives an image encoding stream including image encoding data and the parameter. The parameter changing unit changes the parameter received by the data receiving unit, that is, the parameter specified for encoding performed by a sender, to a value suitable for image recognition performed in the subsequent stage. The decoding unit generates the image decoding data by decoding the received image encoding data according to the changed parameter. The image recognition unit performs image recognition on the image decoding data.
    Type: Grant
    Filed: June 27, 2015
    Date of Patent: January 24, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenichi Iwata, Tetsuya Shibayama, Katsushige Matsubara, Ren Imaoka, Seiji Mochizuki