Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract: A waveguide includes a narrow waveguide, wide waveguides, and tapered waveguides. A width Ww of the wide waveguides is wider than A width Wn of the narrow waveguide. The tapered waveguides have their width continuously varying so as to couple the narrow waveguide and the wide waveguides, respectively. Assuming a length of the waveguide as L and an area as S, Ks=S/(Wn·L) and 1<ks?1.5 are satisfied.

Abstract: An object is to provide a reliability-improved semiconductor device having a MONOS memory that rewrites data by injecting carriers into a charge storage portion. When a memory gate electrode having a small gate length is formed in order to overlap a carrier injection position in write operation with that in erase operation, each into an ONO film including a charge storage portion, the ONO film is formed in a recess of a main surface of a semiconductor substrate for securing a large channel length. In a step of manufacturing this structure, control gate electrodes are formed by stepwise processing of a polysilicon film by first and second etching and then, the recess is formed in the main surface of the semiconductor substrate on one side of the control gate electrode by second etching.

Abstract: A voltage monitoring module includes a first terminal configured to be coupled to a high-potential-side terminal of a first battery cell, and a second terminal configured to be coupled to a low-potential-side of the first battery cell.

Abstract: A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an electron supply layer, a mesa type cap layer, a source electrode, a drain electrode and a gate insulating film covering the cap layer, and a gate electrode formed on the gate insulating film, is configured as follows. The cap layer and the gate electrode are separated from each other by the gate insulating film, and side surfaces of the cap layer, the side surfaces being closer to the drain electrode and the source electrode, have tapered shapes. For example, a taper angle (?1) of the side surface of the cap layer (mesa portion) is equal to or larger than 120 degrees. By this configuration, a TDDB life can be effectively improved, and variation in an ON-resistance can be effectively suppressed.

Abstract: The invention addresses providing a semiconductor device that enables to reduce noise simultaneous with switching. A driver IC which is a semiconductor device includes a drive circuit which drives a control terminal of a PMOS drive stage which is a switching element, a noise detection circuit which detects noise in an output signal when switching (turning) the PMOS drive stage on or off, and a control circuit which control driving by the drive circuit based on the detected noise.

Abstract: The performance of a semiconductor device is improved. An emitter electrode is coupled to a P-type body region and an N+-type emitter region of a linear active cell region via a contact groove formed on an interlayer insulating film and is coupled to a P-type body region of a linear hole connector cell region via a contact groove. The contact grooves arranged in the linear hole connector cell region are shorter than the contact groove in plan view.

Abstract: In a system for performing clock generation for each semiconductor device, synchronization between the semiconductor devices is achieved without causing a count value in a counter to be discontinuously changed.

Abstract: In a memory, multiple pieces of entry data sorted in ascending or descending order are stored associated with addresses. With whole addresses for storing the multiple pieces of entry data as an initial search area, the search circuit repeatedly performs a search operation for comparing entry data stored in a central address of the search area with the search data, outputting the address as a search result in the case of a match, and narrowing the search area for the next search based on a magnitude comparison result in the case of a mismatch.

Abstract: A processor includes a plurality of processing sections, each of which executes a predetermined process. A plurality of fault detecting circuits are respectively provided for the plurality of processing sections, to detect a fault in one of the plurality of processing sections as a fault processing section to generate a fault detection signal. A fault monitoring and control section controls a normal processing section as at least one of the plurality of processing sections other than the fault processing section to execute a relieving process in response to the fault detection signal. The relieving process is determined based on a process load of the fault processing section, a process load of the normal processing section, and priority levels of processes to be executed by the fault processing section and the normal processing section.

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract: A semiconductor device includes a mode determination unit configured to determine a power mode based on a temperature of the semiconductor device and a reference temperature, the power mode including one of a first mode which sets the operating frequency of the operation clock to be a first operating frequency and a second mode which sets the operating frequency of the operation clock to be a second operating frequency, and output a control signal according to the power mode to a clock generating unit.

Abstract: An object of the present invention is to efficiently perform a data load process or a data store process between a memory and a storage unit in a processor. The processor includes: a plurality of storage units associated with a plurality of data elements included in a data set; and a control unit that reads the plurality of data elements stored in adjacent storage areas from a memory, in which a plurality of the data sets is stored, collectively for respective data sets, sorts the respective read data elements to a storage unit corresponding to the data element among the plurality of storage units, and writes the data elements to the respective data sets.

Abstract: In order to improve the performance of a semiconductor device, a p type impurity is ion implanted into an area of an n type semiconductor film that is epitaxially grown over a p type semiconductor substrate, and the p type impurity is not ion implanted into an area of the n type semiconductor film, which is adjacent to the area in which the p type impurity is ion implanted. In this way, a p? type drift layer comprised of the area in which the p type impurity is introduced, as well as an n? type semiconductor region comprised of the area in which the p type impurity is not introduced are formed.

Abstract: A semiconductor device includes: a semiconductor chip including a level shift circuit to output a high amplitude signal from an input of a logical signal, the level shift circuit including a series coupling circuit coupled to a second power supply, a control circuit coupled to the series coupling circuit for controlling the series coupling circuit based on the logical signal, and a first potential conversion circuit coupled between the series coupling circuit and the control circuit and coupled to a first power supply. The series coupling circuit includes a plurality of first MOS transistors coupled in series between the second power supply and a reference power supply, and a plurality of second MOS transistors coupled in series between the second power supply and the reference power supply in series with the plurality of first MOS transistors.

Abstract: Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.

Abstract: The RISC data processor is based on the idea that in case that there are many flag-generating instructions, the number of flags generated by each instruction is increased so that a decrease of flag-generating instructions exceeds an increase of flag-using instructions in quantity, thereby achieving the decrease in instructions. With the data processor, an instruction for generating flags according to operands' data sizes is defined. To an instruction set handled by the RISC data processor, an instruction capable of executing an operation on operand in more than one data size, which performs a process identical to an operation process conducted on the small-size operand on low-order bits of the large-size operand, and generates flags capable of coping with the respective data sizes regardless of the data size of each operand subjected to the operation is added. Thus, the reduction in instruction code space of the RISC data processor tight in instruction code space can be achieved.

Abstract: Image processing is made efficient. An image processing apparatus according to an embodiment includes a line memory, a plurality of pipelines, and a line memory control circuit that controls data reading from the line memory to processing units. The processing unit includes a first operator that performs a first arithmetic operation, a second operator which performs a second arithmetic operation based on first intermediate data based on an arithmetic operation result of the first operator and which calculates second intermediate data according to the first intermediate data of when peripheral pixels are sequentially changed, third operators which perform a third arithmetic operation based on the first intermediate data and which calculate third intermediate data according to the first intermediate data of when the peripheral pixels are sequentially changed, and delay elements that delay the third intermediate data.

Abstract: In a semiconductor device including a resistance element, an electrostatic protection element, including a parasitic bipolar transistor having the resistance element as a component, is provided. That is, instead of providing a dedicated electrostatic protection element in a semiconductor device, a function as an electrostatic protection element is also achieved by using a resistance element provided in a semiconductor device.

Abstract: The invention provides a semiconductor device capable of diagnosing communication network quality. Disclosed is a semiconductor device that is coupled to a light source, the semiconductor device including a signal processing unit that is coupled to an interface module and transmits and receives a command signal to increase or decrease illumination intensity of the light source and a deterioration detector that detects deterioration of the interface module, based on whether or not change timing of a signal representing data of a command signal received by the interface module falls within a predetermined interval.