Abstract: The speed of pen position detection is improved without increasing the circuit area and the current consumption. A sampling circuit samples a signal and outputs sampling data. A arithmetic circuit calculates a real part and an imaginary part of the sampling data. The arithmetic circuit classifies the real part of the sampling data into one of a plurality of groups and classifies the imaginary part of the sampling data into one of the groups according to an order of output of the sampling data from the sampling circuit. Then, the arithmetic circuit adds together real parts of sampling data belonging to a group and adds together imaginary parts of sampling data belonging to a group for each of the groups, and calculates amplitude and phase of the signal by using an addition result of the real parts and an addition result of the imaginary parts of each of the groups.

Abstract: A semiconductor device includes: a first power source (PS1) pad supplied with a PS1 voltage; a PS1 line connected to the PS1 pad; a first ground line (G1); an output circuit operated using the PS1 voltage; a second power source (PS2) pad supplied with a PS2 voltage; a PS2 line connected to the PS2 pad; a second ground line (G2); a signal line connected to an output end of the output circuit; an input circuit connected to the signal line at an input end receiving a signal from the output end and operated using the PS2 voltage; a main protection circuit unit providing discharge routes between the PS1 pad and G1, G1 and G2, and G2 and the PS2 pad; and a sub protection circuit unit. The output circuit includes: a circuit element arranged between the PS1 line and the signal line and able to function as a resistive element.

Abstract: The present invention provides an optical semiconductor device in which damage of a lens when being mounted and mounting displacement due to suction failures of a chip can be suppressed. An optical semiconductor device according to an embodiment includes: a semiconductor substrate having a first surface and a second surface facing the first surface; an electrode formed over the first surface of the semiconductor substrate; an optical element that is electrically coupled to the electrode and is formed in the semiconductor substrate; and a lens arranged on the second surface side of the optical element. A concave part is formed in the second surface of the semiconductor substrate, and the lens is arranged at the bottom of the concave part. A top part on the second surface side of the lens is located on the first surface side relative to the second surface located around the concave part.

Abstract: A migration of a program executing entity between a plurality of processors can be efficiently performed. A semiconductor device 1 includes a first processor 10, a second processor 20, and an external register 4 provided outside the processors. The first processor 10 includes a control circuit 12, an arithmetic circuit 14, and an internal storage circuit 16 provided inside the first processor 10. The second processor 20 includes a control circuit 22, an arithmetic circuit 24, and an internal storage circuit 26 provided inside the second processor 20. The control circuits 12 and 22 control execution of a program. The arithmetic circuits 14 and 24 perform an operation related to the program by using the external register 4. The external register 4 stores operation data related to the operation performed in the arithmetic circuits 14 and 24. The internal storage circuits 16 and 26 store execution state data regarding an execution state of the program.

Abstract: For example, a semiconductor device capable of achieving a high performance applicable to an SR motor is provided. The semiconductor device includes a chip mounting portion TAB1 on which a semiconductor chip CHP1 having an IGBT is mounted, and a chip mounting portion TAB2 on which a semiconductor chip CHP2 having a diode is formed. The semiconductor device also includes a lead LD1A electrically connected to an emitter electrode pad EP of the semiconductor chip CHP1 via a clip CLP1, and a lead LD1B electrically connected to an anode electrode pad ADP of the semiconductor chip CHP2 via a clip CLP2. At this time, the chip mounting portion TAB1 is separated electrically from the chip mounting portion TAB2, and the clip CLP1 is separated electrically from the clip CLP2.

Abstract: A memory cell includes a control gate electrode and a memory gate electrode. The control gate electrode is formed over the upper surface and the sidewall of a fin FA including apart of a semiconductor substrate. The memory gate electrode is formed over one side surface of the control gate electrode and the upper surface and the sidewall of the fin through an ONO film, in a position adjacent to the one side surface of the control gate electrode. Further, the control gate electrode and the memory gate electrode are formed of n-type polycrystalline silicon. A first metal film is provided between the gate electrode and the control gate electrode. A second metal film is provided between the ONO film and the memory gate electrode. A work function of the first metal film is greater than a work function of the second metal film.

Abstract: A resistance change element includes first and second electrodes spaced apart from each other, a metal material layer adjacent to the first electrode, an oxide layer adjacent to each of the metal material layer and the first electrode, and a resistance change layer disposed continuously between the second and first electrodes and between the second electrode and the oxide layer. The resistance change layer is made of a metal oxide. The metal material layer is made of a metal or a metal compound. The oxide layer is made of an oxide of the material forming the metal material layer. The first electrode is made of ruthenium, ruthenium oxide, iridium, iridium oxide, platinum, gold, or copper. A free energy of oxide formation of the oxide forming the oxide layer is higher than a free energy of oxide formation of the oxide forming the resistance change layer.

Abstract: To raise confidentiality of the value stored in the ROM, in an IC having a built-in or an externally-attached ROM storing a value (program and/or data) encrypted using a predetermined cryptographic key. The IC includes the ROM storing the encrypted value (program and/or data), a unique code generating unit, and a decrypting unit. The unique code generating unit generates a unique code specifically determined by production variation. The decrypting unit calculates a cryptographic key on the basis of the generated unique code and a correction parameter, and decrypts the encrypted value read out from the ROM by using the calculated cryptographic key. The correction parameter is preliminarily calculated outside the IC, on the basis of an initial unique code generated from the unique code generating unit immediately after production of the IC, and the predetermined cryptographic key used for encryption of the value to be stored in the ROM.

Abstract: To provide a semiconductor device having improved reliability by preventing, in a split-gate MONOS memory comprised of a fin type transistor, unbalanced injection distribution of electrons into a charge accumulation film due to the shape of the fin. A memory gate electrode configuring a memory cell is formed over a fin. The impurity concentration of a portion of this memory gate electrode contiguous to an ONO film that covers the upper surface of the fin is made lower than that of a portion of the memory gate electrode contiguous to an ONO film that covers the side surface of the fin.

Abstract: A semiconductor device including an isolation insulating film having a first thickness that is located between a drain region and a source region; a gate electrode formed over a region located between the isolation insulating film and the source region and that includes a part serving as a channel; an interlayer insulating film formed so as to cover the gate electrode; and a contact plug formed to reach the inside of the isolation insulating film while penetrating the interlayer insulating film, wherein the contact plug includes a buried part that is formed from the surface of the isolation insulating film up to a depth corresponding to a second thickness thinner than the first thickness.

Abstract: A power supply circuit according to an embodiment of the invention includes: voltage sources; voltage control circuits that boost an input voltage; and a voltage source connection switch that connects at least one of the voltage sources to one of the voltage control circuits. For example, the voltage source connection switch connects, to the voltage control circuit, a voltage source having a voltage lower than a predetermined reference voltage among the voltage sources, and connects, to the voltage control circuit, a voltage source having a voltage equal to or higher than the determined reference voltage among the voltage sources.

Abstract: In a semiconductor device, an abnormality monitor unit detects whether abnormal leakage current has been generated from a first functional module or a second functional module on the basis of a comparison between a change in voltage at a first node between the first functional module and a first power switch when the first power switch is in an off state and a change in voltage at a second node between the second functional module and a second power switch when the second power switch is in the off state.

Abstract: A semiconductor device includes a drive control circuit which drives a gate terminal of an IGBT. The drive control circuit includes a state machine control circuit, a base data memory and a current drive circuit which drives the IGBT on the basis of driving current information stored in the base data memory. The state machine control circuit reads out driving current information for rising stored in the base data memory a plurality of times in a predetermined time period and drives the current drive circuit at rising of a PWM signal, and reads out driving current information for falling stored in the base data memory a plurality of times in a predetermined time period and drives the current drive circuit at falling of the PWM signal.

Abstract: A semiconductor device includes a semiconductor substrate including a main surface, a plurality of first projecting portions which include portions of the semiconductor substrate provided in a first region of the semiconductor substrate to extend in a first direction along the main surface of the semiconductor substrate and to be spaced apart from each other in a second direction, orthogonal to the first direction, along the main surface of the semiconductor substrate, a first isolation region provided between the first projecting portions adjacent to each other, and first and second transistors provided in and over an upper part of each of the first projecting portions which is exposed from an upper surface of the first isolation region to be adjacent to each other in the first direction.

Abstract: Degradation of a reception performance by an image signal is reduced. A semiconductor device includes: an oscillation circuit configured to generate a local signal; a mixer configured to multiply a reception signal by the local signal; an analog filter configured to filter a signal output from the mixer; an AD converter configured to digitalize a signal that has passed through the analog filter to generate a first signal; a digital filter configured to filter a signal that has passed through the AD converter to generate a second signal; a power comparator configured to detect the power difference between the first signal and the second signal; a register configured to store a theoretical power difference; and a determination unit configured to determine a frequency of the local signal based on the power difference from the theoretical power difference.

Abstract: The reliability and performances of a semiconductor device having a nonvolatile memory are improved. A selection gate electrode is formed over a semiconductor substrate via a first insulation film. Over the opposite side surfaces of the selection gate electrode, second insulation films of sidewall insulation films are formed. Over the semiconductor substrate, a memory gate electrode is formed via a third insulation film having a charge accumulation part. The selection gate electrode and the memory gate electrode are adjacent to each other via the second insulation film and the third insulation film. The second insulation film is not formed under the memory gate electrode. The total thickness of the second insulation film and the third insulation film interposed between the selection gate electrode and the memory gate electrode is larger than the thickness of the third insulation film interposed between the semiconductor substrate and the memory gate electrode.

Abstract: A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.

Abstract: A band gap reference circuit includes a first bipolar transistor and a second bipolar transistor that are coupled to a first power supply terminal and a second power supply terminal, each base of the first bipolar transistor and the second bipolar transistor being coupled to an output terminal, a first resistor that is coupled to the second power supply terminal and the first bipolar transistor, a second resistor and a third resistor that are coupled to an end of the first bipolar transistor of the first resistor and the second bipolar transistor in series, a ninth resistor that is coupled to the first power supply terminal and a collector of the first bipolar transistor, a tenth resistor that is coupled to the first power supply terminal and a collector of the second bipolar transistor, and an amplifier is coupled to the collector of the first bipolar transistor.

Abstract: Germanium (Ge) contamination to a semiconductor manufacturing apparatus is suppressed. Germanium is a dissimilar material in a silicon semiconductor process. A semiconductor device is provided with a Ge photodiode including an n-type germanium layer, and a plug capacitively coupled to the n-type germanium layer. In other words, the n-type germanium layer of the Ge photodiode and the plug are not in direct contact with each other but are capacitively coupled to each other.

Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.