Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.

Abstract: A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control circuit. The address control circuit controls the first and second word lines independently of each other on the basis of address signals that are respectively supplied to the first and second address terminals in a normal operation mode, and activates both of the first and second word lines that are coupled to the same memory cell on the basis of the address signal that is supplied to one of the first and second address terminals in a disturb test mode.

Abstract: A semiconductor device including a field-effect transistor having source and drain source regions, first and second gate electrodes and a protective diode connected to the transistor. The first gate electrode is formed over a first gate insulating film in a lower part of a trench. The second gate electrode is formed over a second gate insulating film in an upper part of the trench. The first gate electrode includes a first polysilicon film, and the second gate electrode includes a second polysilicon film, wherein an impurity concentration of the first polysilicon film is lower than an impurity concentration of the second polysilicon film.

Abstract: A semiconductor device PKG includes a semiconductor chip CP, a lead LD3, a wire BW5 electrically connecting a pad electrode PD2 of the semiconductor chip CP to the lead LD3, a wire BW3 electrically connecting a pad electrode PD3 of the semiconductor chip CP to the lead LD3, and a sealing body sealing them with a resin. The semiconductor chip CP includes internal circuits 5b and 5c, and a switch circuit unit SW. Signal transmission is possible between the internal circuit 5c and the pad electrode PD3. The switch circuit unit SW is a circuit capable of being set in a first state in which signal transmission is possible between the internal circuit 5b and the pad electrode PD2, and in a second state in which signal transmission is not possible between the internal circuit 5b and the pad electrode PD2. The switch circuit unit SW is fixed to the second state during operation of the semiconductor device PKG.

Abstract: A loop antenna 1 includes: a first electrode terminal 2c; a second electrode terminal 2d arranged to make a pair with the first electrode terminal 2c; and a loop-shaped member 2 which has one end connected to the first electrode terminal 2c and the other end connected to the second electrode terminal 2d, is wound a plurality of times, and is made of a conductive material. The first electrode terminal 2c and the second electrode terminal 2d are arranged so as to make a pair with respect to a center line 3 of the loop-shaped member 2. Further, the loop-shaped member 2 includes a first loop-shaped member 2a, a second loop-shaped member 2b, and an intersection part 2e. The intersection part 2e is arranged on the center line 3 in a plan view, and the loop-shaped member 2 is continuously connected and formed to be symmetrical with respect to the center line 3.

Abstract: In a non-insulated DC-DC converter having a circuit in which a power MOS?FET high-side switch and a power MOS?FET low-side switch are connected in series, the power MOS?FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS?FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS?FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Abstract: The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a high-side switch, a second semiconductor chip including a second field effect transistor for a low-side switch, and a third semiconductor chip including a circuit that controls each of the first and second semiconductor chips are sealed with a sealing portion. A lead electrically connected to a pad of the first semiconductor chip for a source of the first field effect transistor and a lead electrically connected to a back-surface electrode of the second semiconductor chip for a drain of the second field effect transistor are disposed on the same side of the sealing portion in a plan view.

Abstract: In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

Abstract: A bonding pad of a semiconductor chip in a QFP includes, in its exposed portion, a via disposition area comprising: a first segment that connects a corner and a first point; a second segment that connects the corner and a second point; and an arc that connects the first point and the second point and forms a convex shape toward the corner. Further, in a plan view of the bonding pad, at least a part of a via is disposed so as to overlap with the via disposition area.

Abstract: A semiconductor device that includes a memory system is configured to accept input of search data and to search in parallel respective rows of a memory cell array such as a CAM and so forth for data held in a memory. The memory system detects whether an inflow amount of the search data that is input is at least a fixed amount by monitoring a packing ratio of an FIFO buffer that a search command is held. The memory system controls a speed of search processing by dividing the memory cell array into blocks and setting each block as a search processing object in accordance with a result of detection.

Abstract: A semiconductor memory device according to the present invention includes a first memory cell, a second memory cell, a dummy transistor, and a voltage control circuit. The first memory cell has a first transistor that is coupled to a first word line, a first source line, and a bit line. The second memory cell has a second transistor that is coupled to a second word line, a second source line, and the bit line. The dummy transistor has the same structure as the first transistor and is coupled to a dummy word line, a dummy source line, and a dummy bit line. When a predetermined voltage for writing data into the first memory cell is to be applied to the first word line, the voltage control circuit couples the dummy bit line to the second source line and applies the predetermined voltage to the first dummy word line.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a main surface, the main surface including a first area and a second area, which is different from the first area in a plan view, forming a first trench in the main surface of the semiconductor substrate in the first area, after the forming the first trench, forming a first insulating film on a side wall surface and a bottom face of the first trench, and after the forming the first insulating film, forming a first conductor film over the semiconductor substrate in the first area and a second area to embed a portion of the first conductor film into the first trench through the first insulating film.

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wiring to reduce irregularities caused by the wiring and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

Abstract: Over a semiconductor substrate, a memory gate electrode for a nonvolatile memory cell is formed via a first insulating film having an internal charge storage portion. A dummy control gate electrode is formed so as to be adjacent to the memory gate electrode via a second insulating film. The memory and the dummy control gate electrodes are made of different materials. A third insulating film is formed so as to cover the memory and the dummy control gate electrodes and then polished to expose the memory and the dummy control gate electrodes. Then, etching is performed under a condition in which the memory gate electrode is less likely to be etched than the dummy control gate electrode to remove the dummy control gate electrode. Then, in a trench as a region from which the dummy control gate electrode is removed, a control gate electrode for the memory cell is formed.

Abstract: Current sensing with RDSON correction is disclosed. In an embodiment, a method comprises: measuring an approximate temperature of a MOS transistor switch by a temperature sensor to yield a measured temperature; calculating a corrected temperature from the measured temperature using a stored temperature sensor gain and offset correction function; measuring a gate drive voltage for the MOS transistor; calculating a voltage correction factor using a stored voltage correction function, wherein the stored voltage correction function is a function of the corrected temperature and the gate drive voltage; measuring a RDSON voltage drop across the MOS transistor switch to yield a measured RDSON voltage drop; and calculating the current using the measured RDSON drop and the voltage correction factor.

Abstract: A semiconductor device capable of controlling a memory while preventing the functional deterioration of the memory and reducing the power consumption of the semiconductor device is provided. The semiconductor device includes a first semiconductor chip (logic chip) and a second semiconductor chip (memory chip). The first semiconductor chip includes a plurality of temperature sensors disposed in mutually different places, and a memory controller that controls each of a plurality of memory areas provided in the second semiconductor chip based on output results of a respective one of the plurality of temperature sensors.

Abstract: A level shifter including first and second MOS transistors placed in parallel between a first power supply voltage terminal and a reference voltage terminal, each transistor having a gate connected to a drain of the other transistor, third and fourth MOS transistors placed between the first and second MOS transistors and the reference voltage terminal and having gates respectively supplied with first and second control signals, and fifth and sixth MOS transistors placed between the third and fourth MOS transistors and the reference voltage terminal and having gates respectively supplied with third and fourth control signals, wherein the first to fourth control signals are used to control a conductive/nonconductive state between the first MOS transistor and the reference voltage terminal and a conductive/nonconductive state between the second MOS transistor and the reference voltage terminal.

Abstract: A mesa portion of a semiconductor device, which includes a channel base layer formed of a first nitride semiconductor layer, a channel layer formed of a second nitride semiconductor layer, a barrier layer formed of a third nitride semiconductor layer, a mesa-type fourth nitride semiconductor layer, a gate insulating film that covers the mesa portion, and a gate electrode formed over the gate insulating film, is used as a co-doped layer. The mesa portion is used as the co-doped layer, so that interface charges generated at an interface between the gate insulating film and the mesa portion can be cancelled by p-type impurity or n-type impurity in the co-doped layer and a threshold potential can be improved. Further, the fourth nitride semiconductor layer is n-type until the gate insulating film is formed, and the fourth nitride semiconductor layer is made neutral or p-type after the gate insulating film is formed.

Abstract: A semiconductor device includes a central processing unit and a processor on one semiconductor substrate. The processor includes a buffer for storing a first register setting list and notifies the central processing unit of an access complete signal indicating completion of reading a second register setting list within a memory. The central processing unit changes the second register setting list within the memory based on the access complete signal and notifies the processor of an update request signal. The processor reads the second register setting list changed by the central processing unit into the buffer to update the first register setting list based on the update request information.

Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.