Abstract: A semiconductor device has a p-type metal oxide semiconductor layer; a source electrode connected with the p-type metal oxide semiconductor layer; a drain electrode connected with the p-type metal oxide semiconductor layer; and a gate electrode arranged to oppose to a part of the p-type metal oxide semiconductor layer. The gate electrode and the drain electrode are separated from each other in a top view.

Abstract: A method of manufacturing a semiconductor device includes preparing a lead frame provided with a die pad having an upper surface and a plurality of leads being arranged so as to be aligned on a side of the die pad and each including a wire joint part at a distal end on the side of the die pad, after the preparing the lead frame, mounting a semiconductor chip having a main surface and a plurality of electrode pads formed on the main surface, on the upper surface of the die pad, and after the mounting the semiconductor chip, electrically connecting a first electrode pad among the plurality of electrode pads of the semiconductor chip and a first lead among the plurality of leads to each other via a first wire.

Abstract: To enhance the write speed of a nonvolatile memory. A charge injection/emission part of a nonvolatile memory cell includes an active region having an upper face, a side wall, and a shoulder part connecting the upper face and the side wall, a conductor film covering the upper face and the shoulder part of the active region, and a capacitance insulating film provided between the conductor film and the active region. Furthermore, the active region has a protrusion part constituted of a first concave part with respect to the upper face and a second concave part with respect to the side wall, in the shoulder part.

Abstract: The reliability of a semiconductor device is improved. A probe mark is formed on a probe region of a pad covered with a protective insulating film. And, a pillar-shaped electrode has a first portion formed on an opening region and a second portion that is extended over the probe region from the upper portion of the opening region. At this time, a center position of the opening region is shifted from a center position of the pillar-shaped electrode that is opposed to a bonding finger.

Abstract: The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Abstract: In an IGBT, defects generated by ion implantation for introduction of the P-type collector region or N-type buffer region into the N?-type drift region near the N-type buffer region remain to improve the switching speed, however the leak current increases by bringing a depletion layer into contact with the crystal defects at the off time. To avoid this, an IGBT is provided which includes an N-type buffer region having a higher concentration than that of an N?-type drift region and being in contact with a P-type on its backside, and a defect remaining region provided near the boundary between the N-type buffer region and the N?-type drift region. The N?-type drift region located on the front surface side with respect to the defect remaining region is provided with an N-type field stopping region having a higher concentration than that of the N?-type drift region.

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

Abstract: A timing analysis device includes a storage unit and a processing unit. The processing unit performs storage processing and analysis processing. The storage processing stores circuit information of a circuit to be analyzed, timing constraint information defining timing constraints on the circuit, delay information defining a plurality of delay values associated with a plurality of cells constituting the circuit, and delay upper limit information including at least one delay upper limit for setting an upper limit to the plurality of delay values associated with the plurality of cells into a storage unit. The analysis processing generates a timing analysis result of a circuit to be analyzed, with delay value change processing that changes at least one of the plurality of delay values to the delay upper limit, using the changed delay upper limit in addition to the circuit information, the timing constraint information and the delay information.

Abstract: A battery voltage monitoring apparatus for monitoring an assembled battery voltage, the assembled battery including a plurality of battery cells, the battery voltage monitoring apparatus including a plurality of input terminals, the plurality of input terminals being respectively coupled to the plurality of battery cells through a potential measurement line, a comparator having a hysteresis characteristic and including a first terminal and a second terminal, the second terminal receiving a reference voltage, and a current source, one end of the current source being coupled between one of the plurality of the input terminals and the first terminal.

Abstract: A semiconductor device including a detector to compare an amplitude of an applicable signal with a specified threshold amplitude, and to output a detector output indicating whether or not the amplitude of the applicable signal is above a specified threshold amplitude, and an intermittent operation control circuit that receives the detector output, and also receives a first signal showing which mode among the multiple modes the standby mode state is in, and sets the detector to the on (enable) mode state when the input signal is above the specified threshold amplitude, and in all other cases intermittently operates the detector according to characteristics of the input signal in the mode shown by the applicable first signal.

Abstract: In order to reduce power consumption, a semiconductor device includes an RTC for generating a piece of time information and a first activation signal SW3, a comparator for determining whether the value of an analog input signal exists within a predetermined range, an AD conversion circuit for converting the analog input signal to a digital signal in response to a common activation signal, and a CPU for processing the digital signal in response to the common activation signal. When the analog input signal does not exist within the predetermined rang, the comparator generates the common activation signal. Then, the CPU stores the piece of digital information corresponding to the digital signal as well as the piece of time information from the RTC into a storage circuit.

Abstract: A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling transistor couples a first circuit to a second circuit lower in supply voltage than the first circuit. A second conductivity type region is disposed around the coupling transistor. A part of the field plate electrode partially overlaps with the second conductivity type region. The field plate electrode is electrically coupled to a drain electrode of the coupling transistor at a portion located on the first circuit region side from a center thereof in a width direction of the separation region. A ground potential or a power potential of the second circuit is applied to the field plate electrode at a portion located on the second conductivity type region side from the center.

Abstract: To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a Cu film, an Ni film, and a Pd film which have been formed successively from the side of a semiconductor substrate. The Pd film on the uppermost surface is used as an electrode pad and a bonding wire made of Cu is coupled to the upper surface of the Pd film. The thickness of the Pd film is made smaller than that of the Ni film and the thickness of the Ni film is made smaller than that of the Cu film. The Cu film, the Ni film, and the Pd film have the same pattern shape in a plan view.

Abstract: The present invention is to reduce the possibility that a DC-DC converter stops in the case where supply power is small and load current is large. Output terminals use a DC output voltage of a DC-DC converter so that an external battery can be charged or power can be supplied to a power-reception-side system on the outside, and a current limiting circuit limits load current of a power supply switch transistor flowing from a converter output terminal to the output terminals. An input voltage detecting circuit detects level of a DC input voltage of an input terminal, generates a detection signal, and supplies the detection signal to the current limiting circuit. In the case where the DC input voltage of the input terminal is at the low level, the current limiting circuit controls the maximum current by current limitation of the power supply switch transistor to a small current.

Abstract: A microcontroller includes a CPU (Central Processing Unit), a data input unit, and an oscillator that supplies a clock signal in response to operational modes of the microcontroller. The operational modes include a STOP mode, a SNOOZE mode and a RUN mode, in the STOP mode, the oscillator and the CPU are stopped, in the RUN mode, the CPU and the data input unit operate using the clock signal supplied from the oscillator, and in the SNOOZE mode, the oscillator starts and supplies the clock signal to the data input unit when the data input unit receives first data, and the microcontroller switches to the RUN mode after the data input unit receives second data using the clock signal.

Abstract: A scan test generation method includes dividing a single clock domain into a plurality of regions; incorporating a test pattern generation control circuit in each of the regions; selecting one of a skewed-load mode and a broadside mode as a test pattern generation mode by the test pattern generation control circuit for each region; generating a test pattern determined based on selected one of the test pattern generation mode for each region; and generating a test pattern such that the skewed-load mode and the broadside mode are mixed in a single clock domain.

Abstract: The speed of task scheduling by a multitask OS is increased. A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and execute a task in accordance with the data in the processing register. The save circuit is provided with a plurality of save registers respectively associated with a plurality of tasks. In executing a predetermined system call, the execution control circuit notifies the task control circuit as such. The task control circuit switches between tasks for execution upon receipt of the system call signal, by saving, in the save register associated with a task being executed, the data in the processing register, selecting a task to be executed next, and loading data in the save register associated with the selected task into the processing register.

Abstract: A USB hub capable of reducing power consumption in a USB system. The USB hub includes an upstream USE port, a downstream USB port, a clock pin that supplies an operation clock to a USE peripheral device, and a hub controller that stops clock supply to the USB peripheral device via the clock pin when a connecting between the upstream USB port and a USB host is disconnected or when the hub controller receives a suspend request to the downstream USB port from the USB host.

Abstract: Manufacturing stability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes the steps of: forming an etching stopper film over a first interlayer insulating film; forming an inorganic insulating film over the etching stopper film; forming a resist film over the inorganic insulating film; selectively etching the etching stopper film and the inorganic insulating film by using the resist film as a mask to form a first opening in the etching stopper film and to form a second opening in the inorganic insulating film; removing the resist film by O2 plasma ashing; forming a second interlayer insulating film over the inorganic insulating film; and etching the second interlayer insulating film to form a wiring groove that is coupled to the second opening, and etching a portion located under the first opening of the first interlayer insulating film to form a via hole.