Abstract: A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a semiconductor chip and an interposer electrically, a second coupling part to couple the interposer and a wiring substrate, and an external terminal formed on the bottom surface of the wiring substrate. The high speed transmission path includes a first transmission part located in the interposer to couple the first and second coupling parts electrically and a second transmission part located in the wiring substrate to couple the second coupling part and the external terminal electrically. The high speed transmission path is coupled with a correction circuit in which one edge is coupled with a branching part located midway in the second transmission part and the other edge is coupled with a capacitative element, and the capacitative element is formed in the interposer.

Abstract: According to one embodiment, a semiconductor device includes external terminals supplied with the pair of voltage signals based on a detection result of a resolver through first and second input resistances, respectively, an operation amplifier configured to amplify a potential difference between the pair of the voltage signals supplied to the external terminals, a feedback resistance disposed between an output terminal of the operation amplifier and one of two input terminals thereof, switches disposed between the two input terminals of the operation amplifier and the external terminals, respectively, and a short-circuit failure detection circuit configured to detect whether or not a short-circuit failure has occurred in the resolver based on a voltage level of each of the external terminals in a state where the switches are in an off-state.

Abstract: To start power supply at a high current without applying USB Power Delivery, a power supply system includes a power supply device having a first USB connector conforming to the USB Type-C standard, and a power receiving device having a second USB connector conforming to the USB Type-C standard. The second USB connector includes a high current notification pin for notifying that it is possible to receive power at a high current greater than a predetermined reference current. When the second USB connector is coupled to the first USB connector, the power receiving device notifies the power supply device of the fact that it is possible to receive power at a high current greater than the predetermined reference current, through the high current notification pin. When receiving the notification, the power supply device determines that it is possible to start power supply to the receiving device at a high current.

Abstract: A semiconductor device is comprised of a memory cell array with multiple memory cells arranged in a matrix, multiple bit-line pairs provided for each memory cell column in the memory cell array, multiple input/output circuits provided respectively corresponding to the multiple bit-line pairs, and as interface control circuit that controls the data input/output to the multiple input/output circuits when performing the data write and data read for each memory cell row in a normal mode. The interface control circuit is comprised of a selection circuit. When the data write and data read are performed for each memory cell row in a test mode, the selection circuit selects the data input/output to one of first input/output circuit and a second input/output circuit, respectively corresponding to a first memory cell included in the memory cell row and a second memory cell adjoining the first memory cell, according to a test address.

Abstract: A motor control system includes a first MCU and a second MCU. The first MCU includes an error detection unit, a resolver digital converter, and a first PWM generation unit. The resolver digital converter includes an encoder unit, which generates encoder pulses based on angle information and outputs the encoder pulses to the second MCU. The error detection unit outputs an error signal to the second MCU, when an error is detected in the first MCU. The first MCU controls the resolver digital converter to operate using a backup clock supplied from the second MCU.

Abstract: A first comb portion of an n-type well region and a second comb portion of a p? drift region mesh with each other in plan view. A pn junction of the n-type well region and the p? drift region thus has a zigzag shape in plan view. The pn junction formed of the n-type well region and the p? drift region extends from a main surface toward a bottom surface of the isolation trench along a source-side wall surface of an isolation trench.

Abstract: Characteristics of a semiconductor device using a nitride semiconductor are improved. A semiconductor device of the present invention includes a buffer layer, a channel layer, a barrier layer, a mesa-type 2DEG dissolving layer, a source electrode, a drain electrode, a gate insulating film formed on the mesa-type 2DEG dissolving layer, and an overlying gate electrode. The gate insulating film of the semiconductor device includes a sputtered film formed on the mesa-type 2DEG dissolving layer and a CVD film formed on the sputtered film. The sputtered film is formed in a non-oxidizing atmosphere by a sputtering process using a target including an insulator. This makes it possible to reduce positive charge amount at a MOS interface and in gate insulating film and increase a threshold voltage, and thus improve normally-off characteristics.

Abstract: A super junction structure having a high aspect ratio is formed. An epitaxial layer is dividedly formed in layers using the trench fill process, and when each of the layers has been formed, trenches are formed in that layer. For example, when a first epitaxial layer has been formed, first trenches are formed in the epitaxial layer. Subsequently, when a second epitaxial layer has been formed, second trenches are formed in the epitaxial layer. Subsequently, when a third epitaxial layer has been formed, third trenches are formed in the third epitaxial layer.

Abstract: When a trench that penetrates a semiconductor substrate in a scribe region in a solid-state imaging element of a back side illumination type, occurrence of contamination of the solid-state imaging element caused by an etching step for foaming the trench or a dicing step for singulating a semiconductor chip is prevented. When a silicide layer that covers a surface and the like of an electrode of a transistor is formed, in order to prevent formation of the silicide layer that covers a main surface of the semiconductor substrate in the scribe region, the main surface of the semiconductor substrate is covered with an insulation film before a forming step for the silicide layer.

Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Abstract: A computing control device includes extracting a node having a plurality of processing functions having accuracies different from one another from a graph; calculating a required accuracy of a node subsequent to the node that has been extracted; selecting a processing function having a minimum accuracy equal to or higher than the required accuracy that has been calculated from among the plurality of processing functions included in the node that has been extracted; and setting the processing function that has been selected as the processing function of the node that has been extracted.

Abstract: On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points.

Abstract: To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

Abstract: Devices between which packets are transmitted and received include mutually corresponding packet counters. The same random number value is given to the packet counters as their initial values and the packet counters are updated with packet transmission/reception. The transmission-side device generates a MAC value, draws out part thereof on the basis of a counted value of its own packet counter, sets it as a divided MAC value, generates a packet by adding the value to a message and transmits the packet onto a network. The reception-side device generates a MAC value on the basis of the message in the received packet, draws out part thereof on the basis of a counted value of its own packet counter, compares the part with the divided MAC value in the received packet and thereby performs message authentication.

Abstract: A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.

Abstract: A semiconductor device includes a data processing unit that processes input data and outputs processed data, a logic inversion unit that receives the processed data, inverts the processed data based on a determination result signal to be transmitted to a data bus, and an inversion determination unit that compares the input data which has not been processed by the data processing unit with the output data of the logic inversion unit corresponding to a preceding input data, and generates the determination result signal based on a comparison result.

Abstract: There are included a standard deviation calculation unit that receives a plurality of acceleration data and calculates a standard deviation of the plurality of acceleration data for each specified time period, an average calculation unit that receives the plurality of acceleration data and calculates an average value of the acceleration data for each specified time period, a phase estimation unit that estimates a phase of the average value in a space having a first coordinate axis and a second coordinate axis by using the average value when the standard deviation is smaller than a specified threshold, and a phase correction unit that performs phase correction of the average value by using the estimated phase.

Abstract: There is a need to provide a microcomputer capable of eliminating an external terminal for endian selection. Flash memory includes a user boot area for storing a program executed in user boot mode and corresponding endian information and a user area for storing a program executed in user mode and corresponding endian information. A data transfer circuit reads endian information stored in the user boot area or the user area in accordance with operation mode and supplies the endian information to a CPU before reset release of the CPU. Accordingly, an external terminal for endian selection can be eliminated.

Abstract: In a semiconductor device according to an embodiment, a second semiconductor chip is mounted on a first rear surface of a first semiconductor chip. Also, the first rear surface of the first semiconductor chip includes a first region in which a plurality of first rear electrodes electrically connected to the second semiconductor chip via a protrusion electrode are formed and a second region which is located on a peripheral side relative to the first region and in which a first metal pattern is formed. In addition, a protrusion height of the first metal pattern with respect to the first rear surface is smaller than a protrusion height of each of the plurality of first rear electrodes with respect to the first rear surface.