Abstract: Degradation of reliability of a semiconductor device is prevented. An electrode pad included mainly of aluminum is formed over amain surface of a semiconductor wafer. Subsequently, a first insulating member and a second insulating member are formed over the main surface of the semiconductor wafer so as to cover the electrode pad, and thereafter an opening portion that exposes a surface of the electrode pad is formed in the first insulating member and the second insulating member by a dry etching method using an etching gas including a halogen-based gas. Thereafter, an oxide film with a thickness of 2 nm to 6 nm is formed over the exposed surface of the electrode pad by performing a heat treatment at 200° C. to 300° C. in an air atmosphere, and then the semiconductor wafer is stored.

Abstract: A circuit includes a memory cell array which includes: a plurality of memory cells; a plurality of word lines coupled to the memory cells, respectively, and a plurality of bit lines coupled to the memory cells, an address control circuit which includes: a first latch circuit into which a first address signal is input and from which a first output signal is output; a selection circuit into which a second address signal and the first output signal are input and which selects the first output signal or the second address signal for outputting the first output signal or the second address signal as a second output signal; a second latch circuit into which the second output signal is input and from which a third output signal is output; a decode circuit which decodes the third output signal and outputs a fourth output signal; and a word line drive circuit.

Abstract: The reliability of a semiconductor device is improved. A contact trench for coupling a field plate and a field limiting ring situated at the corner part of a semiconductor device is formed of a first straight line part and a second straight line part arranged line symmetrically with respect to the crystal orientation <011>. Respective one ends of the first straight line part and the second straight line part are coupled at the crystal orientation <011>, and the first straight line part and the second straight line part are set to extend in different directions from the crystal orientation <010> and the crystal orientation <011>.

Abstract: The present power transmission device performs a power transmission process for transmitting power in a wireless manner through electromagnetic field resonance coupling using a resonance circuit. In a case where a resonance frequency of the resonance circuit set to be the same as a frequency of a power transmission signal which is output as transmission power is deviated during transmission of the power, the present power transmission device detects a direction in which the resonance frequency is deviated and controls the power transmission process on the basis of a detection result thereof. Consequently, it is possible to determine not only whether or not a foreign substance is present in a power transmission region but also determines whether or not the foreign substance influences wireless power transmission with high accuracy, and thus reliability of the wireless power transmission system can be improved.

Abstract: It is possible to reduce power consumption of a pulsimeter while suppressing a degradation in an accuracy of measuring pulse. A pulsimeter (1) includes a light emitter (10), a photodetector (12), an AD converter (14), a frequency analyzing unit (15), and an adjusting unit (17). The light emitter (10) emits light to a blood vessel of a measurement target. The photodetector (12) detects light emitted by the light emitter (10) via the blood vessel. The AD converter (14) analog/digital converts an output signal of the photodetector (12). The frequency analyzing unit (15) frequency-analyzes data converted by the AD converter (14). The adjusting unit (17) adjusts an amount of light emitted by the light emitter (10) based on the analysis result by the frequency analyzing unit (15).

Abstract: To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed.

Abstract: A selection decoder controls levels of a plurality of selection signals based on an address bit having at least one or more bits. A memory module is selected when its corresponding selection signal is at an activated level, and data can be read and written therein. A failure determination unit determines whether or not the selection decoder is in a failed state based on the levels of the plurality of selection signals.

Abstract: The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.

Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.

Abstract: In order to quickly and reliably establish link up, when a communication device detects power on or link down, an idle signal generation circuit generates an idle signal. Then, an I/F circuit transmits the idle signal to a communication device which is a communication partner through a selection circuit. Further, the I/F circuit transmits and receives learning signals to and from the communication device which is a communication partner. A Step 1 learning circuit, a Step 2 learning circuit, and a Step 3 learning circuit establish link up by using the learning signals. When not receiving a signal from a link detection circuit indicating that link up is established, a reset mask circuit transmits a reset signal generated by a reset signal generation circuit, to the Step 1 learning circuit, the Step 2 learning circuit, and the Step 3 learning circuit to allow them to learn again.

Abstract: The present invention: makes it possible to improve the reliability of a semiconductor device; and provides a method of manufacturing the semiconductor device comprising the steps of (a) providing a semiconductor wafer having a pad electrode, a first conductive layer comprised of copper, a photoresist film, and a second conductive layer comprised of gold, (b) forming a protective film comprised of iodine on the surface of the second conductive layer, (c) removing the photoresist film, (d) irradiating the protective film with argon ions and removing the protective film, and (e) bringing a part of a bonding wire into contact with the surface of the second conductive layer.

Abstract: A semiconductor device according to the present invention includes: a through via formed to penetrate a semiconductor substrate; first and second buffer circuits; a wiring forming layer formed in an upper layer of the semiconductor substrate; a connecting wiring portion formed in an upper portion of the through via assuming that a direction from the semiconductor substrate to the wiring forming layer is an upward direction, the connecting wiring portion being formed on a chip inner end face that faces the upper portion of the semiconductor substrate at an end face of the through via; a first path connecting the first buffer circuit and the through via; and a second path connecting the second buffer circuit and the through via. The first path and the second path are electrically connected through the connecting wiring portion.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a plurality of gate electrodes, forming a first insulating film over the plurality of gate electrodes such that the first insulating film is embedded in a space between the plurality of gate electrodes, forming a second insulating film over the first insulating film, forming a third insulating film over the second insulating film, forming a photosensitive pattern over the third insulating film, performing etching using the photosensitive pattern as a mask to form a trench extending through the first to third insulating films and reaching a semiconductor substrate, removing the photosensitive pattern, performing etching using the exposed third insulating film as a mask to extend the trench in the semiconductor substrate, removing the third and second insulating films, and forming a fourth insulating film in the trench and over the first insulating film.

Abstract: According to one embodiment, a PLL circuit includes: a digital phase comparator that captures an instantaneous value of a reference clock signal, which is a digital since wave, in synchronization with a feedback clock signal, and detects a phase difference between the reference clock signal and the feedback clock signal based on the captured instantaneous value; a control voltage generation unit that generates a control voltage according to the phase difference; a voltage control oscillator that generates an output clock signal having a frequency according to the control voltage; a frequency divider that divides a frequency of the output clock signal to generate the feedback clock signal; and a control unit that amplifies the reference clock signal to be supplied to the digital phase comparator with an amplification factor according to the phase difference.

Abstract: Provided is a semiconductor device including nonvolatile memory cells each including a FinFET having excellent memory characteristics. The semiconductor device includes a semiconductor substrate, memory cells each formed in the semiconductor substrate and having a split-gate structure including an opposed-gate selection gate electrode, a memory gate electrode, and a pair of terminals, and a word line driver circuit which supplies a selection voltage to a selection gate electrode of the selected one of the memory cells and supplies a non-selection voltage to the selection gate electrode of the non-selected one of the memory cells. The word line driver circuit supplies, as the non-selection voltage, a voltage which is negative or positive relative to a potential in the semiconductor substrate so as to bring a selection transistor corresponding to the selection gate electrode of the non-selected memory cell into an OFF state.

Abstract: To achieve a semiconductor device equipped with a low ON voltage and high load short circuit withstand trench gate IGBT. A collector region on a back surface of a semiconductor substrate is comprised of a relatively lightly-doped P+ type first collector region and a relatively heavily-doped P++ type second collector region. The P++ type second collector region includes, in plan view, interfaces between a first trench having therein a first linear trench gate electrode and an N+ type emitter region formed on the side surface of the first trench and between a second trench having therein a second linear trench gate electrode and an N+ type emitter region formed on the side surface of the second trench. This enables electrons injected from the surface side of the semiconductor substrate to reach the P++ type second collector region and offset, with them, holes injected from the back surface side of the semiconductor substrate.

Abstract: There was a problem that it was difficult for a semiconductor device in the related art to increase the switching frequency of a step-up circuit, and it was difficult to stabilize an output current and an output voltage. A semiconductor device controls a step-up circuit including an inductor and a drive transistor to drive the inductor. The semiconductor device calculates upper and lower limits which determine the variable range of an input current, based on an output current and an input voltage, controls the switch timing of the drive transistor based on the relation between the upper and lower limits and the magnitude of the input current, and at the same time, corrects the upper and lower limits to be calculated, based on the magnitude of the difference between the output current and a target output current value as an ideal value of the output current.

Abstract: A semiconductor device (10) includes a transmitting circuit (12) that converts transmission data into a transmission signal with a specified frequency, an amplifier (13) that amplifies a power of the transmission signal, a matching circuit (14) that converts the transmission signal from a balanced signal to an unbalanced signal, and a filter circuit (14) that restricts a frequency band of the transmission signal. The matching circuit includes a primary inductor and a secondary inductor, the filter circuit includes an inductor for a filter, and the primary inductor, the secondary indictor and the inductor for a filter are wound substantially concentrically on one plane.

Abstract: The present invention solves a problem that the phases of clocks obtained by frequency-dividing PLL clocks output from local PLL circuits cannot be made the same in a plurality of data transfer blocks. A local PLL circuit outputs a PLL clock obtained by multiplying a common external clock. A frequency divider outputs a feedback clock obtained by frequency-dividing the PLL clock to the local PLL circuit. An FIFO buffer temporarily holds data input from the outside. The FIFO buffer outputs the held data on the basis of a frequency-divided PLL clock. A clock generator generates a frequency-divided PLL clock obtained by frequency-dividing the PLL clock. The clock generator controls the phase of the frequency-divided PLL clock on the basis of a common start signal.

Abstract: A semiconductor die is disclosed upon which is formed direct current (DC) isolated first and second circuits. The first circuit is configured for electrical connection to a first ground. The second circuit is configured for electrical connection to a second ground. The first and second grounds can be at different potentials. The first and second circuits were formed using front end of line (FEOL) and back end of line (BEOL) processes. The first circuit includes a plurality of first devices, such as transistors, which were formed during the FEOL process, and the second circuit includes only second devices, such as transistors, which were formed during the BEOL process.