Abstract: When a control circuit has received a first erase command, the control circuit controls performing a first pre-write process to allow a first storage device and a second storage device to have threshold voltages, respectively, both increased, and the control circuit thereafter controls performing an erase process to allow the first storage device and the second storage device to have their respective threshold voltages both decreased to be smaller than a prescribed erase verify level. When the control circuit has received a second erase command, the control circuit controls performing a second pre-write process to allow one of the first storage device and the second storage device to have its threshold voltage increased, and control circuit subsequently controls performing the erase process.

Abstract: A semiconductor integrated circuit device includes a component built-in board in which at least a first core layer on which a first electronic component is mounted, a second core layer on which a second electronic component is mounted, an adhesive layer arranged between the first core layer and the second core layer, and wiring layers are stacked; a third electronic component mounted in a first core layer side of the component built-in board and electrically connected to the at least one of the first and second electronic components through the wiring layers; and an external connection terminal formed in a second core layer side of the component built-in board and electrically connected to at least one of the first and second electronic components.

Abstract: In an LDMOS having an element isolation region of an STI structure, there is prevented an occurrence of insulation breakdown which might be caused when electrons generated in a semiconductor substrate near an edge portion of a bottom face of the element isolation region are poured into a gate electrode. Immediately over an upper surface of an offset region adjacent to the element isolation region embedded in a main surface of the semiconductor substrate between a source region and a drain region, there is provided a trench penetrating a silicon film forming the gate electrode. As a consequence, the silicon film and a metal film for filling the trench form the gate electrode.

Abstract: The present invention provides a method of manufacturing a semiconductor device to improve the manufacturing yield of the semiconductor device. The manufacturing method includes the steps of: forming a groove extending in a first direction (y direction) across a first power transistor formation region and a second power transistor formation region, in a back surface of a semiconductor wafer; filling the groove with a conductor film by forming the conductor film on the back surface in which the groove is formed; and exposing the back surface of the semiconductor wafer by removing a portion of the conductor film.

Abstract: An object is to prevent a short failure in magnetic tunnel junction and thereby suppress a semiconductor device having a magnetic memory cell from having deteriorated reliability. First, a data reference layer and a cap layer are patterned. After formation of an oxygen-free first insulating film on their side walls, a base layer, a data recording layer, and a tunnel barrier layer are patterned. During patterning of the base layer, data recording layer, and tunnel barrier layer, adhesion of a metal substance of the data reference layer and the cap layer to the side wall of the tunnel barrier layer can be prevented because the data reference layer and the cap layer are covered by the first insulating film.

Abstract: A semiconductor device having a memory cell includes: a first gate electrode formed on a semiconductor substrate via a first insulating film; a second gate electrode formed on the semiconductor substrate via the second insulating film having a charge storage portion inside so as to be adjacent to the first gate electrode; a third insulating film interposed between the first gate electrode and the second gate electrode; a first source/drain region formed on a main surface of the semiconductor substrate; a first silicide layer formed in contact with an upper surface of the first source/drain region; a second silicide layer formed in contact with an upper surface of the first gate electrode; and a third silicide layer formed in contact with an upper surface of the second gate electrode. The first to third silicide layers contain platinum.

Abstract: A method of manufacturing a semiconductor device includes forming a reference pattern in an inspection pattern formation region, forming a first mask layer over a semiconductor substrate, while forming a first inspection pattern in the inspection pattern formation region, and measuring a first amount of misalignment of the first inspection pattern with respect to the reference pattern. The method further includes implanting ions into the semiconductor substrate using a first mask layer, removing the first mask layer and the first inspection pattern and then forming a second mask layer over the semiconductor substrate, while forming a second inspection pattern in the inspection pattern formation region, and measuring a second amount of misalignment of the second inspection pattern with respect to the reference pattern. In plan view, the second inspection pattern is larger than the first inspection pattern and covers the entire region where the first inspection pattern is formed.

Abstract: The present invention makes it possible to form a circuit configuration that is capable of executing a keyword search at an increased speed while suppressing an increase in the memory capacity of a content-addressable memory. A semiconductor device according to an aspect of the present invention searches an input data string for a predesignated keyword, and includes a first content-addressable memory that stores a partial keyword corresponding to a predetermined number of data beginning with the first data of the keyword, a second content-addressable memory that stores the entirety of the keyword, and a control circuit that is coupled to the first content-addressable memory and to the second content-addressable memory. When a portion matching the partial keyword is detected in the input data string by a search in the first content-addressable memory, the second content-addressable memory executes a search on search data extracted from the input data string.

Abstract: A provided semiconductor device includes a Ge photodiode having proper diode characteristics. A groove is provided on a germanium growth protective film, a p-type silicon layer, and a first insulating film from the top surface of the germanium growth protective film without reaching the major surface of a semiconductor substrate. An i-type germanium layer and an n-type germanium layer are embedded in the groove with a seed layer interposed between the layers and the groove, the seed layer being made of amorphous silicon, polysilicon, or silicon germanium. The i-type germanium layer and the n-type germanium layer do not protrude from the top surface of the germanium growth protective film, thereby forming a flat second insulating film having a substantially even thickness on the n-type germanium layer and the germanium growth protective film.

Abstract: A semiconductor device includes: a first substrate; a surface insulating film formed over an upper surface of the first substrate; a BOX layer formed over the surface insulating film; an optical waveguide made of an SOI layer formed on the BOX layer; and a first interlayer insulating film formed over the BOX layer so as to cover the optical waveguide. The semiconductor device further includes: a trench formed in the surface insulating film and the first substrate below the optical waveguide; and a cladding layer made of a buried insulating film buried in the trench. A thickness of the BOX layer is 1 ?m or less, and a distance from an interface between the optical waveguide and the BOX layer to a bottom surface of the trench is 2 ?m or more.

Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.

Abstract: According to an aspect, a semiconductor device and an IO-cell include a plurality of first power supply lines and a plurality of second power supply lines alternately arranged in a first direction, the first and second power supply lines each being supplied with electric power in which the voltage of the electric power supplied to the first power supply is different from that supplied to the second power supply, and a third power supply line formed in a wiring layer different from a wiring layer in which the first and second power supply lines are arranged, the third power supply line being connected to adjacent first power supply lines among the plurality of first power supply lines through a via, in which all of the first, second and third power supply lines are formed so as to extend in a second direction perpendicular to the first direction.

Abstract: A semiconductor device includes a power device and a temperature detection diode. The semiconductor device has a device structure configured to insulate between a power lien of the power device and the temperature detection diode.

Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor chip formation region, a chip internal circuit provided within the semiconductor chip formation region of the semiconductor substrate, a signal transmitting/receiving unit which is provided within the semiconductor chip formation region of the semiconductor substrate, transmits/receives a signal to/from an outside in a non-contact manner by one of electromagnetic induction and capacitive coupling, and transmits/receives a signal to/from the chip internal circuit through electrical connection to the chip internal circuit, and a power receiving inductor which has a diameter provided along an outer edge of the semiconductor chip formation region of the semiconductor substrate so as to surround the chip internal circuit and the signal transmitting/receiving unit, receives a power supply signal from the outside in the non-contact manner, and is electrically connected to the chip internal circuit.

Abstract: An arithmetic device which controls a parallel arithmetic operation includes a global memory, a plurality of compute units, each of the compute units including a local memory and a plurality of processing elements, and each of the processing elements including a private memory and processing data blocks stored in the private memory, an attribute group holding unit which includes a specific attribute which includes a parameter indicative of a size of the data block, an arithmetic attribute which includes a parameter indicating whether the data block is a data relevant to processing, and indicating a transfer order when the data block is data relevant to processing, and a policy attribute which includes a parameter indicative of how to execute a transfer of the data block and how to execute processing of the data block.

Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes a pixel including a first active region where a photodiode and a transfer transistor are formed and a second active region for supplying a grounding potential. Over a p-type semiconductor region in the second active region, a plug for supplying the grounding potential is disposed. In an n-type semiconductor region for a drain region of the transfer transistor formed in the first active region, a gettering element is introduced. However, in the p-type semiconductor region in the second active region, the gettering element is not introduced.

Abstract: A semiconductor device includes a substrate, a circuit having a transistor formed on the substrate, an oscillation circuit generating a frequency signal, a substrate voltage generation circuit generating a substrate voltage in accordance with the frequency signal from the oscillation circuit, and a control circuit varying a frequency of the frequency signal from the oscillation circuit during a stand-by period of the circuit.

Abstract: There is a problem in related-art semiconductor devices that the chip size of a semiconductor device having an active Miller clamp function cannot be reduced. According to one embodiment, a semiconductor device is configured to, when a power device is turned on or off, monitor a gate voltage Vg of the power device, set a predetermined range within a transition range, the transition range being a range within which the gate voltage Vg changes, change, when the gate voltage Vg is within the predetermined range, the gate voltage Vg of the power device by using a predetermined number of constant-current circuits, and change, when the gate voltage Vg is outside the predetermined range, the gate voltage Vg by using a larger number of constant-current circuits than the number of constant-current circuits that are used when the gate voltage Vg is within the predetermined range.

Abstract: A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.

Abstract: To provide a highly reliable semiconductor device having both an improved breakdown voltage and a reduced withstand voltage leakage current. An intermediate resistive field plate is comprised of a first intermediate resistive field plate coupled, at one end thereof, to an inner-circumferential-side resistive field plate and, at the other end, to an outer-circumferential-side resistive field plate and a plurality of second intermediate resistive field plates. The first intermediate resistive field plate has a planar pattern that is equipped with a plurality of first portions separated from each other in a first direction connecting the inner-circumferential resistive field plate to the outer-circumferential-side resistive field plate and linearly extending in a second direction orthogonal to the first direction, and repeats reciprocation along the second direction.