Abstract: A method of evaluating a natural frequency of a piezoelectric vibrator including a vibrating membrane and a piezoelectric element, includes: transmitting a drive signal to the piezoelectric element for a certain period of time so as to allow the vibrating membrane to vibrate; acquiring information about a power-generating wave of the piezoelectric vibrator after stopping the transmission of the drive signal to the piezoelectric element; and determining a frequency of the drive wave at which a value of a voltage of the power-generating wave is maximum as the natural frequency of the piezoelectric vibrator, based on the information about the power-generating wave.

Abstract: A micro pump includes: a vibrating membrane on which a piezoelectric element is stacked; an upper space provided in contact with an upper surface of the vibrating membrane; and a lower space provided in contact with a lower surface of the vibrating membrane, wherein by displacing the vibrating membrane toward the upper space, a fluid flows out from the upper space to an outside and flows in from the outside to the lower space, and wherein by displacing the vibrating membrane toward the lower space, the fluid flows out from the lower space to the outside and flows in from the outside to the upper space.

Abstract: A nitride semiconductor device includes an electron transit layer that is formed of a nitride semiconductor, an electron supply layer that is formed on the electron transit layer, and formed of a nitride semiconductor and that has a recess which reaches the electron transit layer from a surface, a thermal oxide film that is formed on the surface of the electron transit layer exposed within the recess, a gate insulating film that is embedded within the recess so as to be in contact with the thermal oxide film, a gate electrode that is formed on the gate insulating film and that is opposite to the electron transit layer across the thermal oxide film and the gate insulating film, and a source electrode and a drain electrode that are provided on the electron supply layer at an interval such that the gate electrode intervenes therebetween.

Abstract: A semiconductor device includes a semiconductor substrate, a first electroconductive member that is formed on the semiconductor substrate and that has a first linear portion extending along a principal surface of the semiconductor substrate, and an organic insulation layer that is formed on the semiconductor substrate and that covers the first electroconductive member, and the first linear portion includes a first side edge portion formed by a curve that is alternately bent to one side and to an opposite side of a direction intersecting a longitudinal direction of the first linear portion in a plan view.

Abstract: A semiconductor device includes a semiconductor layer that has a principal surface, a first conductive layer that is formed on the principal surface of the semiconductor layer, a first insulating portion that is formed on the principal surface of the semiconductor layer so as to cover the first conductive layer and that includes a first insulating layer of at least three or more layers, a second insulating portion that is formed on the first insulating portion, that has a dielectric constant differing from a dielectric constant of the first insulating layer, and that includes a second insulating layer not included in the first insulating portion, and a second conductive layer that is formed on the second insulating portion, that faces the first conductive layer through the first insulating portion and the second insulating portion, and that is connected to a potential differing from a potential of the first conductive layer.

Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

Abstract: This power supply IC is a semiconductor integrated circuit device serving as a main part for controlling a switching power supply and is formed by integrating a feedback resistor and an output feedback control unit on a single semiconductor substrate, said feedback resistor generating a feedback voltage by dividing the output voltage of the switching power supply (or the induced voltage appearing across an auxiliary winding provided on the primary side of a transformer included in an insulation-type switching power supply), said output feedback control unit performing output feedback control of the switching power supply in accordance with the feedback voltage. The feedback resistor is a polysilicon resistor having a withstand voltage of 100 V or more. A high-voltage region having higher withstand voltage in the substrate thickness direction than the other region is formed in the semiconductor substrate, and the feedback resistor is formed on the high-voltage region.

Abstract: A switching power supply device includes first to fourth switches sequentially connected in series, an inductor, a first capacitor whose first end is connected to a connection node of the first switch and the second switch and whose second end is connected to a connection node of the third switch, the fourth switch, and the inductor, a second capacitor whose first end is connected to a connection node of the second switch and the third switch, and a controller that controls switching on and off of the first to fourth switches. In at least one of a first pair configured with the first switch and the third switch and a second pair configured with the second switch and the fourth switch, the controller shifts a timing of switching from off to on between two switches.

Abstract: A semiconductor light-emitting device includes: a board including a front surface, a back surface facing an opposite side of the front surface, a first wiring pattern formed on the front surface, and a second wiring pattern formed on the side of the back surface with respect to the first wiring pattern; and a light-emitting element, a switching element, and a capacitor, which are electrically connected to one another by both the first wiring pattern and the second wiring pattern. Among the light-emitting element, the switching element, and the capacitor, a first predetermined element and a second predetermined element are arranged in a first direction and the second predetermined element and a third predetermined element are arranged in a second direction. The second wiring pattern forms a second current path opposite to a direction of a first current path. The second current path overlaps the first current path.

Abstract: A semiconductor device includes a semiconductor chip, a first conductive film formed on a first principal surface of the semiconductor chip, a fourth conductive film formed on a second principal surface of the semiconductor chip, a third impurity region formed in the semiconductor chip, a vertical-type semiconductor element structure which includes a gate trench formed in an active region and arrayed at a cell pitch and allows a current to flow between the first conductive film and the fourth conductive film, a first outer peripheral trench which is annular and formed in the outer peripheral region, and a plurality of second outer peripheral trenches which are annular and formed in the outer peripheral region further outside than the first outer peripheral trench, in which a first outer peripheral pitch between the first outer peripheral trench and the second outer peripheral trench is not less than 2 times and not more than 4 times the cell pitch.

Abstract: The present disclosure provides an electronic device. The electronic device includes a first inorganic film, a second inorganic film covering the first inorganic film, and an opening. The opening is formed in the second inorganic film to partially expose the first inorganic film. The opening has a wall surface curved in a wavy line shape in a plan view.

Abstract: A semiconductor device, includes: a semiconductor substrate having first and second main surfaces; and first and second polysilicon layers doped with impurity, wherein the semiconductor substrate includes a diffusion layer doped with impurity, the diffusion layer is located between the first main surface and the second main surface, first and second grooves are formed on the first main surface in spaced-apart relationship along a first direction in a plan view, the first and second grooves each extend along a second direction orthogonal to the first direction in a plan view and extend toward the second main surface to reach the diffusion layer in a cross-sectional view orthogonal to the second direction, the first and second polysilicon layers are embedded in the first and second grooves, respectively, and lower ends of the first and second polysilicon layers are electrically connected to each other by the diffusion layer.

Abstract: A semiconductor device includes an electric conductor, a semiconductor element, and a bonding layer. The electric conductor has a main surface and a rear surface opposite to the main surface in a thickness direction. The semiconductor element includes a main body and electrodes. The main body has a side facing the main surface of the conductor, and the electrodes each protrude toward the main surface from the side of the main body to be electrically connected to the main surface. The bonding layer is held in contact with the main surface and the electrodes. Each electrode includes a base portion in contact with the main body, and a columnar portion protruding toward the main surface from the base portion to be held in contact with the bonding layer, which is a sintered body of a metal powder.

Abstract: In order both to accommodate instantaneous current as well as overcurrent protection in accordance with the load, an overcurrent protection circuit has: a threshold value generation unit that, in accordance with a threshold value control signal, switches between setting an overcurrent detection threshold value to a first set value (? Iref) and a second set value (? Iset) lower than the first set value; an overcurrent detection unit that compares a sense signal in accordance with the current being monitored and the overcurrent detection value and generates an overcurrent protection signal; a reference value generation unit that generates a reference value (? Iset) in accordance with the seconds set value; a comparison unit that compares the sense signal and the reference value, and generates a comparison signal; and a threshold value control unit that monitors the comparison signal, and generates a threshold value control signal.

Abstract: A semiconductor device includes a data bus, a data memory, a selector, a processor, and a debug controller. The selector is configured to be controlled by the debug controller to be in either a first selecting state in which the processor transmits a first signal to the data bus and a second selecting state in which the debug controller transmits a second signal to the data bus. The debug controller is configured to control the state of the selector based on the reception state of a predetermined command from an external device as well as the states of a read enable signal and a write enable signal from the processor such that, when the selector is in the second selecting state, the debug controller accesses the data bus via the selector.

Abstract: A semiconductor device includes a semiconductor element, a first lead (1), a plurality of second leads and a sealing resin. The first lead includes a mounting portion mounting the semiconductor element, four connecting portions extending from four corners of the mounting portion, respectively, and four first terminal portions connected to front ends of the connecting portions, respectively. A part of each first terminal portion is exposed from the sealing resin. The second leads are arranged in a plural quantity between adjacent first terminal portions when viewed in a thickness direction. Each second lead includes a second terminal portion having a part exposed from the sealing resin, and a joining portion extending from the second terminal portion toward the mounting portion. A connecting portion width dimension of the connecting portion is greater than a joining portion width dimension of the joining portion of the second lead adjacent to the connecting portion.

Abstract: A semiconductor device is adapted for controlling energization of a heating element that performs printing. The semiconductor device includes: a strobe signal input unit receiving a printing strobe signal that causes the heating element to generate heat for printing; a preheating strobe generation circuit generating a preheating strobe signal that causes the heating element to preheat by compressing a waveform of the printing strobe signal in a time axis direction; and an output controller outputting a control signal that controls energization of the heating element based on the printing strobe signal and the preheating strobe signal.

Abstract: Semiconductor device A1 includes: first terminal 201A and second terminal 201B; first switching element 1A including first gate electrode 12A, first source electrode 13A and first drain electrode 14A; and second switching element 1B including second gate electrode 12B, second source electrode 13B and second drain electrode 14B. First switching element 1A and second switching element 1B are connected in series to each other between first terminal 201A and second terminal 201B. Semiconductor device A1 includes first capacitor 3A connected in parallel to first switching element 1A and second switching element 1B between first terminal 201A and second terminal 201B. First switching element 1A and second switching element 1B are aligned in y direction. First capacitor 3A overlaps with at least one of first switching element 1A and second switching element 1B as viewed in z direction. These arrangements serve to suppress surge voltage.

Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.

Abstract: The present disclosure provides a current detection circuit having a high detection precision. The current detection circuit includes: a current output type differential amplifier; a first input resistor, configured to be connected between a first input end of the differential amplifier and a first current sense terminal; a second input resistor, configured to be connected between a second input end of the differential amplifier and a second current sense terminal; an output resistor, configured to be connected to an output end of the differential amplifier; a first feedback current path, configured to allow a first feedback current to flow between the first input end and the output end of the differential amplifier; and a second feedback current path, configured to allow a second feedback current to flow between the second current sense terminal and the output end of the differential amplifier.