Abstract: Temporary substrates may include a bonding surface prepared for receiving an additional substrate that will transfer a thin layer. Such substrates may include a principal part or support and a surface layer thereon with the surface layer having a plurality of inserts therein. The inserts are made of a material having a coefficient of thermal expansion that is significantly different from that of the material constituting the surface layer. Processing methods for transferring a selected portion of an original substrate may involve such temporary substrates and productions methods may produce such temporary substrates.

Abstract: Methods of forming ternary III-nitride materials include epitaxially growing ternary III-nitride material on a substrate in a chamber. The epitaxial growth includes providing a precursor gas mixture within the chamber that includes a relatively high ratio of a partial pressure of a nitrogen precursor to a partial pressure of one or more Group III precursors in the chamber. Due at least in part to the relatively high ratio, a layer of ternary III-nitride material may be grown to a high final thickness with small V-pit defects therein. Semiconductor structures including such ternary III-nitride material layers are fabricated using such methods.

Abstract: The present disclosure concerns a method of detaching a layer to be detached from a donor substrate, comprising the following steps: a) assembling the donor substrate and a porous substrate, b) application of a treatment of chemical modification of the crystallites, the chemical modification being adapted to generate a variation of the volume of the crystallites, the volume variation generates deformation in compression or in tension of the porous substrate, the deformation in compression or in tension generates a stress in tension or in compression in the donor substrate, which causes fracture in a fracture plane, the fracture plane delimiting the layer to be detached, the stress leading to the detachment of the layer to be detached from the donor substrate.

Abstract: The disclosure relates to a process for manufacturing a composite structure, the process comprising the following steps: a) providing a donor substrate and a carrier substrate; b) forming a dielectric layer; c) forming a covering layer; d) forming a weakened zone in the donor substrate; e) joining the carrier substrate and the donor substrate via a contact surface having an outline; f) fracturing the donor substrate via the weakened zone, steps b) and e) being executed so that the outline is inscribed in the outline, and step c) being executed so that the covering layer covers the peripheral surface of the dielectric layer.

Abstract: The invention relates to a sense amplifier for sensing and amplifying data stored in a memory cell, the sense amplifier being connected between a bit line (BL) and a reference bit line complementary (/BL) to the first bit line and comprising: a sense circuit (SC) capable of providing an output indicative of the data stored in the memory cell; and a precharge and decode circuit (PDC) comprising a pair of dual gate transistors (T5, T6) for precharging the first and second bit lines during a precharge operation and for transferring the output provided by the sense circuit to a data line (LIO,/LIO) during a read operation.

Abstract: A method for measuring defects in a silicon substrate obtained by silicon ingot pulling, wherein the defects have a size of less than 20 nm. The method includes applying a first defect consolidation heat treatment to the substrate at a temperature of between 750° C. and 850° C. for a time period of between 30 minutes and 1 hour to consolidate the defects; applying a second defect enlargement heat treatment to the substrate at a temperature of between 900° C. and 1000° C. for a time period of between 1 hour and 10 hour hours to enlarge the defects to a size of greater than or equal to 20 nm, with the enlarged defects containing oxygen precipitates; measuring size and density of the enlarged defects in a surface layer of the substrate; and calculating the initial size of the defects on the basis of the measurements of the enlarged defects.

Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

Abstract: A method of preventing microcavity formation in a bonding layer of a composite structure resulting from creep and thermal expansion due to high temperature exposure of the composite structure. The method includes the steps of providing a thin film with a thickness of 5 micrometers or less; providing a bonding layer of oxide with a thickness that is equal to or greater than the thickness of the thin film with the bonding layer formed by low pressure chemical vapor deposition. The thin film or support substrate have a mean thermal expansion coefficient of 7×10?6 K?1 or more. The thin film, bonding layer and support substrate combine to reduce stress in and plastic deformation of the bonding layer during exposure to high temperatures of more than approximately 900° C. to thus prevent microcavities from appearing in the bonding layer.

Abstract: Interposers for use in the fabrication of electronic devices include semiconductor-on-insulator structures having fluidic microchannels therein. The interposers may include a multi-layer body in which a semiconductor material is bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel may extend in a lateral direction through at least one of the layer of dielectric material and the semiconductor material. The interposers may include redistribution layers and electrical contacts on opposing sides thereof. Semiconductor structures include one or more semiconductor devices coupled with such interposers. Such interposers and semiconductor structures may be formed by fabricating a semiconductor-on-insulator type structure using a direct bonding method and defining one or more fluidic microchannels at a bonding interface during the direct bonding process.

Abstract: This process comprises steps of: a) providing a first substrate comprising the active layer made of a first material of Young's modulus E1 and of thickness h1; b) providing a second substrate made of a second material of Young's modulus E2 and of thickness h2; c) bending the first substrate and the second substrate such that they each have a curved shape of a radius of curvature R; d) joining the second substrate to the active layer such that the second substrate closely follows the shape of the first substrate; and e) re-establishing the initial at-rest shape of the second substrate, the process being noteworthy in that the second material of the second substrate is a flexible material respecting the relationship E2/E1<10?2, in that the thickness of the second substrate respects the relationship h2/h1?104, and in that the radius of curvature respects the relationship R = h 2 2 ? ? ? .

Abstract: Embodiments of the invention relate to a process for fabricating a silicon-on-insulator structure comprising the following steps: providing a donor substrate and a support substrate, only one of the substrates being covered with an oxide layer; forming, in the donor substrate, a weak zone; plasma activating the oxide layer; bonding the donor substrate to the support substrate in a partial vacuum; implementing a bond-strengthening anneal at a temperature of 350° C. or less causing the donor substrate to cleave along the weak zone; and carrying out a heat treatment at a temperature above 900° C. A transition from the temperature of the bond-strengthening anneal to the temperature of the heat treatment may be achieved at a ramp rate above 10° C./s.

Abstract: The present invention relates to a register cell comprising one output node, at least two power supply nodes, and a first flash transistor and a second flash transistor, wherein the register cell is configured so that the output node can be driven by at least one of the power supply nodes as a function of the value stored in at least one of the flash transistors. The invention further relates to an FPGA comprising the register cell.

Abstract: The invention relates to a charge pump circuit comprising an input node for inputting a voltage to be boosted; an output node for outputting a boosted voltage; a plurality of pumping stages connected in series between the input node and the output node, each pump stage comprising at least one charge transfer transistor, wherein the at least one charge transfer transistor is a double-gate transistor comprising a first gate for turning the transistor on or off according to a first control signal applied to the first gate and a second gate for modifying the threshold voltage of the transistor according to a second control signal applied to the second gate, wherein the first and second control signals have the same phase.

Abstract: The present invention relates to a process for realizing a connecting structure in a semiconductor substrate, and the semiconductor substrate realized accordingly. The semiconductor substrate has at least a first surface, and is foreseen for a 3D integration with a second substrate along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value.

Abstract: The invention relates to a method for fabricating a structure including a semiconductor material comprising: a) implanting one or more ion species to form a weakened region delimiting at least one seed layer in a substrate of semiconductor material, b) forming, before or after step a), at least one metallic layer on the substrate in semiconductor material, c) assembling the at least one metallic layer with a transfer substrate, then fracturing the implanted substrate at the weakened region, and d) forming at least one layer in semiconductor material on the at least one seed layer, for example, by epitaxy.

Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

Abstract: Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate a semiconductor substrate by forming a weakened zone in a donor structure at a predetermined depth to define a transfer layer between an attachment surface and the weakened zone and a residual donor structure between the weakened zone and a surface opposite the attachment surface. A metallic layer is formed on the attachment surface and provides an ohmic contact between the metallic layer and the transfer layer, a matched Coefficient of Thermal Expansion (CTE) for the metallic layer that closely matches a CTE of the transfer layer, and sufficient stiffness to provide structural support to the transfer layer. The transfer layer is separated from the donor structure at the weakened zone to form a composite substrate comprising the transfer layer and the metallic layer.

Abstract: The present invention relates to a method for controlling a tracker control unit and, therefore, the tracker device of a solar module of a solar power plant, wherein the tracker device comprises a control unit, an actuator element and a support means for supporting the solar module, comprising the steps of detecting a particular event, interrupting power supply to the control unit of the tracker device for a predetermined time period in reaction to the detection of the particular event, resuming power supply after the predetermined time period and in reaction to the resumed power supply actuating the support means by the actuator element to move the support means into a predetermined position.

Abstract: The invention relates to an electronic device for radiofrequency or power applications, comprising a semiconductor layer supporting electronic components on a support substrate, wherein the support substrate comprises a base layer having a thermal conductivity of at least 30 W/mK and a superficial layer having a thickness of at least 5 ?m, the superficial layer having an electrical resistivity of at least 3000 Ohm·cm and a thermal conductivity of at least 30 W/mK. The invention also relates to two processes for manufacturing such a device.