Patents Assigned to Soitec
  • Patent number: 9437473
    Abstract: A process for separating at least two substrates comprising at least two separation interfaces along one of the interfaces includes, before inserting a blade between the substrate, damaging at least one portion of a peripheral region of a chosen one of the interfaces, then inserting the blade and partially parting the substrates, and applying a fluid in a space between the parted substrates while the blade remains inserted therebetween, and decreasing a rupture energy of the chosen interface by stress corrosion involving breaking of siloxane bonds present at the interface.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: September 6, 2016
    Assignee: SOITEC
    Inventors: Didier Landru, Christophe Figuet
  • Patent number: 9425081
    Abstract: The disclosure relates to a method for implantation of atomic or ionic species into a batch of substrates made of semiconductor material, in which: each substrate made of semiconductor material is positioned on a respective support of a batch implanter, each substrate comprising a thin layer of electrical insulator on its surface; and a dose of at least one ionic or atomic species is implanted over the whole surface of the substrates, through their layer of insulator, so as to form a fragilization region within each substrate and to bound there a thin layer of semiconductor material between the thin layer of insulator and the fragilization region of the substrate, the implantation method being characterized in that, during the method, each support on which a substrate is positioned has at least two separate inclinations with respect to the plane orthogonal to the direction of implantation of the species in order to improve the implantation depth of the species in the substrate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 23, 2016
    Assignee: SOITEC
    Inventors: Nadia Ben Mohamed, Carole David, Camille Rigal
  • Patent number: 9412580
    Abstract: Embodiments of the invention include methods for forming Group III-nitride semiconductor structure using a halide vapor phase epitaxy (HVPE) process. The methods include forming a continuous Group III-nitride nucleation layer on a surface of a non-native growth substrate, the continuous Group III-nitride nucleation layer concealing the upper surface of the non-native growth substrate. Forming the continuous Group III-nitride nucleation layer may include forming a Group III-nitride layer and thermally treating said Group III-nitride layer. Methods may further include forming a further Group III-nitride layer upon the continuous Group III-nitride nucleation layer.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: August 9, 2016
    Assignee: SOITEC
    Inventors: Chantal Arena, Ronald Thomas Bertram, Jr., Ed Lindow, Subhash Mahajan, Fanyu Meng
  • Patent number: 9412904
    Abstract: A device for back-scattering an incident light ray, including: a host substrate; a structured layer; a first face in contact with a front face of the host substrate; a second flat face parallel to the first face; a first material and a second material which form, in a mixed plane, alternating surfaces at least one of whose dimensions is between 300 nm and 800 nm, the mixed plane is between the first and second face of the structured layer; wherein the refractive index of the first and of the second material are different, the structured layer is covered by a specific layer, the specific layer is made of a material which is different from the first and second materials of the structured layer, and the specific layer is crystalline and semi-conductive.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: August 9, 2016
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, Soitec
    Inventors: Yohan Desieres, Philippe Gilet, Pascal Guenard
  • Patent number: 9396987
    Abstract: The invention relates to a method for fabricating a substrate, comprising the steps of providing a donor substrate with at least one free surface, performing an ion implantation at a predetermined depth of the donor substrate to form an in-depth predetermined splitting area inside the donor substrate, and is characterized in providing a layer of an adhesive, in particular an adhesive paste, over the at least one free surface of the donor substrate. The invention further relates to a semiconductor structure comprising a semiconductor layer, and a layer of a ceramic-based and/or a graphite-based and/or a metal-based adhesive provided on one main side of the semiconductor layer.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 19, 2016
    Assignee: Soitec
    Inventor: Oleg Kononchuk
  • Patent number: 9397258
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer, and at least one barrier layer proximate the at least one well layer. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: July 19, 2016
    Assignee: SOITEC
    Inventors: Chantal Arena, Jean-Philippe Debray, Richard Scott Kern
  • Patent number: 9390771
    Abstract: A circuit for sensing a difference in voltage on a pair of dual signal lines comprising a first signal line and a second signal line complementary to the first signal line, comprising: a pair of cross-coupled inverters arranged between the first and the second signal lines, each inverter having a pull-up transistor and a pull-down transistor, the sources of the pull-up transistors or of the pull-down transistors being respectively connected to a first and a second pull voltage signals, a decode transistor having source and drain terminals respectively coupled to one of the first and second signal lines and a gate controlled by a decoding control signal, whereby when the decode transistor is turned on by the decoding control signal, a short circuit is established between the first and the second signal lines through which current flows from one of the first and second pull voltage signals, thereby generating a disturb in between the first and the second pull voltage signals.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: July 12, 2016
    Assignee: Soitec
    Inventors: Richard Ferrant, Roland Thewes
  • Patent number: 9391011
    Abstract: Semiconductor structures are fabricated that include a semiconductor material bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel extends in a lateral direction through the layer of dielectric material between the semiconductor material and the substrate. The at least one fluidic microchannel includes at least one laterally extending section having a transverse cross-sectional shape entirely surrounded by the layer of dielectric material.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: July 12, 2016
    Assignee: Soitec
    Inventor: Mariam Sadaka
  • Patent number: 9368344
    Abstract: Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: June 14, 2016
    Assignee: SOITEC
    Inventor: Chantal Arena
  • Patent number: 9349865
    Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: May 24, 2016
    Assignee: SOITEC
    Inventors: Bich-Yen Nguyen, Mariam Sadaka, Christophe Maleville
  • Patent number: 9343626
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: May 17, 2016
    Assignee: SOITEC
    Inventors: Jean-Philippe Debray, Chantal Arena, Heather McFavilen
  • Patent number: 9343351
    Abstract: This transfer process comprises the following steps: (a) providing a donor substrate and a support substrate; (b) forming an embrittlement region in the donor substrate; (c) forming what is called a bonding layer between the first part of the donor substrate and the support substrate; and (d) assembling the donor substrate to the support substrate, and is noteworthy in that it comprises the following step: (e) exposing, in succession, portions of the embrittlement region to electromagnetic irradiations for an exposure time at a given power density, the exposure time being chosen depending on the thickness of the bonding layer so that the support substrate is thermally decoupled from the first part of the donor substrate, the exposure time being chosen depending on the power density in order to activate kinetics that weaken the embrittlement region.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: May 17, 2016
    Assignee: Soitec
    Inventor: Michel Bruel
  • Patent number: 9337377
    Abstract: Atomic layer deposition (ALD) or ALD-like deposition processes are used to fabricate dilute nitride III-V semiconductor materials. A first composition of process gases may be caused to flow into a deposition chamber, and a group V element other than nitrogen and one or more group III elements may be adsorbed over the substrate (in atomic or molecular form). Afterward, a second composition of process gases may be caused to flow into the deposition chamber, and N and one or more group III elements may be adsorbed over the substrate in the deposition chamber. An epitaxial layer of dilute nitride III-V semiconductor material may be formed over the substrate in the deposition chamber from the sequentially adsorbed elements.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: May 10, 2016
    Assignee: SOITEC
    Inventors: Chantal Arena, Robin Scott, Claudio Canizares
  • Patent number: 9330958
    Abstract: The invention relates to a process for fabricating a heterostructure comprising at least one thin layer and a carrier substrate made of a semiconductor, the process comprising: bonding a first substrate made of a single-crystal first material, the first substrate comprising a superficial layer made of a polycrystalline second material, to a second substrate so that a bonding interface is created between the polycrystalline layer and the second substrate; removing from the free surface of one of the substrates, called the donor substrate, a thickness thereof so that only a thin layer is preserved; generating a layer of amorphous semiconductor material between the first substrate and the bonding interface by amorphization of the layer of polycrystalline material; and crystallizing the layer of amorphous semiconductor material, the newly crystallized layer having the same orientation as the adjacent first substrate.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: May 3, 2016
    Assignee: SOITEC
    Inventor: Gweltaz Gaudin
  • Patent number: 9324911
    Abstract: Dilute nitride III-V semiconductor materials may be formed by substituting As atoms for some N atoms within a previously formed nitride material to transform at least a portion of the previously formed nitride material into a dilute nitride III-V semiconductor material that includes arsenic. Such methods may be employed in the fabrication of photoactive devices, such as photovoltaic cells and photoemitters. The methods may be carried out within a deposition chamber, such as a metalorganic chemical vapor deposition (MOCVD) or a hydride vapor phase epitaxy (HVPE) chamber.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: April 26, 2016
    Assignee: Soitec
    Inventors: Chantal Arena, Robin Scott, Claudio Canizares
  • Patent number: 9312339
    Abstract: Methods of fabricating semiconductor structures include forming a plurality of openings extending through a semiconductor material and at least partially through a metal material and deforming the metal material to relax a remaining portion of the semiconductor material. The metal material may be deformed by exposing the metal material to a temperature sufficient to alter (i.e., increase) its ductility. The metal material may be formed from one or more of hafnium, zirconium, yttrium, and a metallic glass. Another semiconductor material may be deposited over the remaining portions of the semiconductor material, and a portion of the metal material may be removed from between each of the remaining portions of the semiconductor material. Semiconductor structures may be formed using such methods.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: April 12, 2016
    Assignee: Soitec
    Inventor: Christiaan J. Werkhoven
  • Patent number: 9306104
    Abstract: The invention relates to a photovoltaic concentrator module with multifunction frame and also to a method for production thereof. The concentrator module has a lens- and a base plate, between which a frame extends. Between the lens plate and the frame and/or the base plate and the frame, two sealing compounds and/or adhesive compounds extend, which compounds differ with respect to their hardening time and/or gas permeability.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: April 5, 2016
    Assignee: SOITEC SOLAR GMBH
    Inventors: Frank Dimroth, Andreas Bett, Christoph Schmidt, Hansjörg Lerchen-Müller
  • Patent number: 9293448
    Abstract: Three-dimensionally integrated semiconductor systems include a photoactive device operationally coupled with a current/voltage converter on a semiconductor-on-insulator (SeOI) substrate. An optical interconnect is operatively coupled to the photoactive device. A semiconductor device is bonded over the SeOI substrate, and an electrical pathway extends between the current/voltage converter and the semiconductor device bonded over the SeOI substrate. Methods of forming such systems include forming a photoactive device on an SeOI substrate, and operatively coupling a waveguide with the photoactive device. A current/voltage converter may be formed over the SeOI substrate, and the photoactive device and the current/voltage converter may be operatively coupled with one another. A semiconductor device may be bonded over the SeOI substrate and operatively coupled with the current/voltage converter.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: March 22, 2016
    Assignee: SOITEC
    Inventors: Bich-Yen Nguyen, Mariam Sadaka
  • Patent number: 9293473
    Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: March 22, 2016
    Assignee: SOITEC
    Inventors: Patrick Reynaud, Sebastien Kerdiles, Daniel Delprat
  • Patent number: 9275892
    Abstract: A method of transferring a layer from a donor substrate onto a receiving substrate comprises ionic implantation of at least one species into the donor substrate and forming a layer of concentration of the species intended to form microcavities or platelets; bonding the donor substrate with the receiving substrate by wafer bonding; and splitting at high temperature to split the layer in contact with the receiving substrate by cleavage, at a predetermined cleavage temperature, at the layer of microcavities or platelets formed in the donor substrate. The method further comprises, after the first implantation step and before the splitting step, ionic implantation of silicon ions into the donor substrate to form a layer of concentration of silicon ions in the donor substrate, the layer of concentration of silicon ions at least partially overlapping the layer of concentration of the species intended to form microcavities or platelets.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: March 1, 2016
    Assignee: SOITEC
    Inventors: Nicolas Daix, Konstantin Bourdelle