Patents Assigned to Soitec
  • Patent number: 9716029
    Abstract: A method for transferring a layer of semiconductor by providing a donor substrate that includes a useful layer of a semiconductor material, a confinement structure that includes a confinement layer of a semiconductor material having a chemical composition that is different than that of the useful layer, and two protective layers of semiconductor material that are distinct from the confinement layer with the protective layers being arranged on both sides of the confinement layer; introducing ions into a donor substrate, bonding the donor substrate to a receiver substrate, subjecting the donor and receiver substrates to a heat treatment that provides an increase in temperature during which the confinement layer attracts the ions in order to concentrate them in the confinement layer, and detaching the donor substrate from the receiver substrate by breaking the confinement layer.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: July 25, 2017
    Assignee: SOITEC
    Inventors: Fabrice Lallement, Christophe Figuet, Daniel Delprat
  • Patent number: 9716164
    Abstract: Methods of forming semiconductor devices include epitaxially growing a III-V base layer over a first substrate in a first deposition chamber. The III-V base layer is transferred from the first substrate to a second substrate, and at least one III-V device layer is epitaxially grown on the III-V base layer in a second deposition chamber separate from the first deposition chamber while the III-V base layer is disposed on the second substrate. The first substrate exhibits an average coefficient of thermal expansion (CTE) closer to an average CTE exhibited by the III-V base layer than an average CTE exhibited by the second substrate. Semiconductor devices may be fabricated using such methods.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: July 25, 2017
    Assignee: SOITEC
    Inventor: Mariam Sadaka
  • Patent number: 9716148
    Abstract: Methods of fabricating semiconductor structures include the formation of molybdenum nitride at one or more surfaces of a substrate comprising molybdenum, and providing a layer of III-V semiconductor material, such as GaN, over the substrate. Semiconductor structures formed by methods described herein may include a substrate comprising molybdenum, molybdenum nitride at one or more surfaces of the substrate, and a layer of GaN bonded to the molybdenum nitride.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 25, 2017
    Assignee: Soitec
    Inventor: Christiaan J. Werkhoven
  • Patent number: 9698063
    Abstract: The invention concerns a method of testing a semiconductor-on-insulator type structure comprising a support substrate, a dielectric layer having a thickness of less than 50 nm and a semiconductor layer, the structure comprising a bonding interface between the dielectric layer and the support substrate or the semiconductor layer or inside the dielectric layer, characterized in that it comprises measuring the charge to breakdown (QBD) of the dielectric layer and in that information is deduced from the measurement relating to the hydrogen concentration in the layer and/or at the bonding interface. The invention also concerns a method of fabricating a batch of semiconductor-on-insulator type structures including carrying out the test on a sample structure from the batch.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: July 4, 2017
    Assignee: SOITEC
    Inventors: Patrick Reynaud, Walter Schwarzenbach, Konstantin Bourdelle, Jean-Francois Gilbert
  • Patent number: 9679777
    Abstract: A method for separating a structure from a substrate through electromagnetic irradiations (EI) belonging to a spectral range comprises the steps of a) providing the substrate, b) forming an absorbent separation layer on the substrate, c) forming the structure to be separated on the separation layer, d) exposing the separation layer to the electromagnetic irradiations (EI) via the substrate such that the separation layer breaks down under the effect of the heat stemming from the absorption, the method being notable in that it comprises a step b1) of forming a transparent thermal barrier layer on the separation layer, the exposure period and the thickness of the thermal barrier layer being adapted such that the temperature of the structure to be separated remains below a threshold during the exposure period, beyond which threshold, faults are likely to appear in the structure.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: June 13, 2017
    Assignee: Soitec
    Inventors: Yann Sinquin, Jean-Marc Bethoux, Oleg Kononchuk
  • Patent number: 9679799
    Abstract: The present disclosure relates to a process for fabricating a plurality of semiconductor-on-insulator structures, the insulator being a layer of silicon dioxide having a thickness smaller than 50 nm, each structure comprising a semiconductor layer placed on the silicon dioxide layer, the fabrication process comprising a step of heat treating the plurality of structures, which heat treatment step is designed to partially dissolve the silicon dioxide layer, the heat treatment step being carried out in a non-oxidizing atmosphere and the pressure of the non-oxidizing atmosphere being lower than 0.1 bar.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: June 13, 2017
    Assignee: SOITEC
    Inventors: Christophe Gourdel, Oleg Kononchuk
  • Patent number: 9659777
    Abstract: The invention relates to a process for stabilizing a bonding interface, located within a structure for applications in the fields of electronics, optics and/or optoelectronics and that comprises an oxide layer buried between an active layer and a receiver substrate, the bonding interface having been obtained by molecular adhesion. In accordance with the invention, the process further comprises irradiating this structure with a light energy flux provided by a laser, so that the flux, directed toward the structure, is absorbed by the energy conversion layer and converted to heat in this layer, and in that this heat diffuses into the structure toward the bonding interface, so as to thus stabilize the bonding interface.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: May 23, 2017
    Assignee: Soitec
    Inventors: Didier Landru, Carole David, Ionut Radu, Lucianna Capello, Yann Sinquin
  • Patent number: 9653536
    Abstract: A method for fabricating a structure comprising, in succession, a support substrate, a dielectric layer, an active layer, a separator layer of polycrystalline silicon, comprising the steps of: a) providing a donor substrate, b) forming an embrittlement area in the donor substrate, c) providing the support structure, d) forming the separator layer on the support substrate, e) forming the dielectric layer, f) assembling the donor substrate and the support substrate, g) fracturing the donor substrate along the embrittlement area, h) subjecting the structure to a strengthening annealing of at least 10 minutes, the fabrication method being noteworthy in that step d) is executed in such a way that the polycrystalline silicon of the separator layer exhibits an entirely random grain orientation, and in that the strengthening annealing is executed at a temperature strictly greater than 950° C. and less than 1200° C.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: May 16, 2017
    Assignee: Soitec
    Inventors: Alexandre Chibko, Isabelle Bertrand, Sylvain Peru, Sothachett Van, Patrick Reynaud
  • Publication number: 20170133347
    Abstract: A manufacturing method including supplying a first substrate including a first face designated front face, the front face being made of a III-V type semiconductor, supplying a second substrate, forming a radical oxide layer on the front face of the first substrate by executing a radical oxidation, assembling, by a step of direct bonding, the first substrate and the second substrate so as to form an assembly including the radical oxide layer intercalated between the first and second substrates, executing a heat treatment intended to reinforce the assembly interface, and making disappear, at least partially, the radical oxide layer.
    Type: Application
    Filed: November 1, 2016
    Publication date: May 11, 2017
    Applicants: Commissariat A L'Energie Atomique et aux Energies Alternatives, SOITEC
    Inventors: Hubert MORICEAU, Bruno IMBERT, Xavier BLOT
  • Patent number: 9646825
    Abstract: The invention relates to a method for fabricating a composite structure comprising a layer to be separated by irradiation, the method comprising the formation of a stack containing: a support substrate formed from a material that is at least partially transparent at a determined wavelength; a layer to be separated; and a separation layer interposed between the support substrate and the layer to be separated, the separation layer being adapted to be separated by exfoliation under the action of radiation having a wavelength corresponding to the determined wavelength. Furthermore, the method comprises, during the step for forming the composite structure, a treatment step modifying the optical properties in reflection at an interface between the support substrate and the separation layer or on an upper face of the support substrate.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: May 9, 2017
    Assignee: SOITEC
    Inventors: Christophe Figuet, Christophe Gourdel
  • Patent number: 9644285
    Abstract: Methods of depositing compound semiconductor materials on one or more substrates include metering and controlling a flow rate of a precursor liquid from a precursor liquid source into a vaporizer. The precursor liquid may comprise at least one of GaCl3, InCl3, and AlCl3 in a liquid state. The precursor liquid may be vaporized within the vaporizer to form a first precursor vapor. The first precursor vapor and a second precursor vapor may be caused to flow into a reaction chamber, and a compound semiconductor material may be deposited on a surface of a substrate within the reaction chamber from the precursor vapors. Deposition systems for performing such methods include devices for metering and/or controlling a flow of a precursor liquid from a liquid source to a vaporizer, while the precursor liquid remains in the liquid state.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: May 9, 2017
    Assignee: SOITEC
    Inventor: Ronald Thomas Bertram, Jr.
  • Patent number: 9640696
    Abstract: Apparatus for the industrial wiring and final testing of photovoltaic concentrator modules, consisting of a module frame, a lens disc, a sensor carrier disc and an electrical line routing arrangement, comprising the following features: a) a laser contact-making device for the contactless connection of connecting lines between the individual sensors and of connecting elements and of collective contact plates, wherein the line routing arrangement on the sensor carrier disc as basic structure has, in each case, five CPV sensors connected in parallel, and these parallel circuits are connected in series, b) a device for testing electrical properties, wherein a specific voltage is applied to CPV sensors themselves, and the light emitted by them via the lenses is detected and assessed, c) a device for testing tightness of finished concentrator modules, wherein compressed air is applied to the modules in the interior and the emission of compressed air is checked.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 2, 2017
    Assignee: SOITEC SOLAR GMBH
    Inventor: Eckart Gerster
  • Patent number: 9640664
    Abstract: The present invention relates to a method for polarizing at least a first finfet transistor and a second finfet transistor, wherein the first finfet transistor has a fin width bigger than the fin width of the second finfet transistor, and both the first finfet transistor and the second finfet transistor have a back gate, and the method comprising applying the same first voltage on the back gate of the first finfet transistor and on the back gate of the second finfet transistor so as to reduce the spread between the off-current value of the first finfet transistor and the off-current value of the second finfet transistor.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: May 2, 2017
    Assignee: Soitec
    Inventor: Franz Hofmann
  • Patent number: 9634182
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: April 25, 2017
    Assignee: SOITEC
    Inventors: Jean-Philippe Debray, Chantal Arena, Heather McFavilen, Ding Ding, Li Huang
  • Patent number: 9620626
    Abstract: Methods of fabricating semiconductor structures involve the formation of fins for finFET transistors having different stress/strain states. Fins of one stress/strain state may be employed to form n-type finFETS, while fins of another stress/strain state may be employed to form p-type finFETs. The fins having different stress/strain states may be fabricated from a common layer of semiconductor material. Semiconductor structures and devices are fabricated using such methods.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: April 11, 2017
    Assignees: SOITEC, STMICROELECTRONICS, INC.
    Inventors: Frédéric Allibert, Pierre Morin
  • Patent number: 9621168
    Abstract: The present invention relates to a look-up table comprising a plurality of register signals (r0-r3); a plurality of inputs signals (A, A?, B, B?); and at least one output signal (Y); and a plurality of pass gates, wherein at least a first pass gate of the plurality of pass gates is controlled by at least a first input signal of the plurality of input signals, and by at least a first register signal, of the plurality of register signals, such that the register signal has priority over the input signal on the operation of the first pass gate.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: April 11, 2017
    Assignee: SOITEC
    Inventor: Richard Ferrant
  • Patent number: 9607879
    Abstract: A process for fabrication of a structure includes assembling at least two substrates. At least one of these two substrates is intended to be used in electronics, optics, optoelectronics and/or photovoltaics. The structure includes at least two separation interfaces extending parallel to the main faces of the structure. The assembling process is carried out with a view to a separation of the structure along one interface selected from the interfaces, the separation being carried out by inserting a blade between the substrates and applying a parting force, via the blade. The interface chosen for the separation is formed so that it is more sensitive than the other interface(s) to stress corrosion. Separation occurs due to the combined action of the parting force and of a fluid capable of breaking siloxane (Si—O—Si) bonds present at the interface. A structure obtained by such a process may be separated along the chosen interface.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: March 28, 2017
    Assignee: SOITEC
    Inventor: Didier Landru
  • Patent number: 9589830
    Abstract: A method for transferring a useful layer onto a support includes the following processes: formation of a fragilization plane through the implantation of light species into a first substrate in such a way as to form a useful layer between this plane and a surface of the first substrate; application of the support onto the surface of the first substrate to form an assembly to be fractured having two exposed sides; thermal fragilization treatment of the assembly to be fractured; and initiation and self-sustained propagation of a fracture wave in the first substrate along the fragilization plane. At least one of the sides of the assembly to be fractured is in close contact, over a contact zone, with an absorbent element suitable for capturing and dissipating acoustic vibrations emitted during the initiation and/or propagation of the fracture wave.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: March 7, 2017
    Assignees: Soitec, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Didier Landru, Oleg Kononchuk, Nadia Ben Mohamed, Damien Massy, Frederic Mazen, Francois Rieutord
  • Patent number: 9590126
    Abstract: The present invention relates to a solar cell assembly that includes a solar cell attached to a bonding pad and a cooling substrate, wherein the bonding pad is attached to a surface of the cooling substrate by a thermally conductive adhesive and electrically contacted to the bonding pad and cooling substrate by a bonding wire. Alternatively, the bonding pad is attached to a surface of the cooling substrate by a thermally and electrically conductive adhesive.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: March 7, 2017
    Assignee: Soitec Solar GmbH
    Inventors: Martin Ziegler, Sascha Van Riesen
  • Patent number: 9583341
    Abstract: A process for transferring a useful layer to a receiver substrate includes providing a donor substrate comprising an intermediate layer, a carrier substrate, and a useful layer. The intermediate layer is free of species liable to degas during a subsequent heat treatment, and is configured to become soft at a temperature. The receiver substrate and the donor substrate are assembled. An additional layer is provided between the receiver substrate and the carrier substrate that comprises chemical species that are susceptible to diffuse into the intermediate layer during the subsequent heat treatment so as to form a weak zone. The heat treatment is carried out on the receiver substrate and the donor substrate at a second temperature higher than the first temperature.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: February 28, 2017
    Assignee: Soitec
    Inventors: Vivien Renauld, Monique Lecomte