Patents Assigned to Soitec
  • Patent number: 9914233
    Abstract: This disclosure relates to a device for separating two substrates to be utilized in electronics, optics, optoelectronics and/or photovoltaics. The device separates the substrates at an interface, the device comprising a holder; a member for retaining the structure, the member being mounted on the holder; a tool for separating the two substrates, also mounted on the holder; and means for moving the separating tool and/or means for moving the retaining member relative to the holder so as to bring them closer together or move them farther apart from each other, preferably over a limited range of travel. This device is noteworthy in that the separating tool comprises a leading edge that has, in cross-section, in succession from its tip or its front edge to its back, a tapered portion that is extended by a flared portion.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: March 13, 2018
    Assignee: SOITEC
    Inventor: Didier Landru
  • Patent number: 9911624
    Abstract: This disclosure relates to a method for dissolving a silicon dioxide layer in a structure, including, from the back surface thereof to the front surface thereof, a supporting substrate, the silicon dioxide layer and a semiconductor layer, the dissolution method being implemented in a furnace in which structures are supported on a support, the dissolution method resulting in the diffusion of oxygen atoms included in the silicon dioxide layer through the semiconductor layer and generating volatile products, and the furnace including traps suitable for reacting with the volatile products, so as to reduce the concentration gradient of the volatile products parallel to the front surface of at least one structure.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: March 6, 2018
    Assignee: SOITEC
    Inventors: Didier Landru, Oleg Kononchuk
  • Patent number: 9911616
    Abstract: The disclosure relates to a process for treating a structure, the structure comprising, from its back side to its front side, a carrier substrate, an insulating layer and a useful layer, the useful layer having a free surface, the structure being placed in an atmosphere containing chemical species, the chemical species being capable of reacting chemically with the useful layer. This treatment process is noteworthy in that the useful layer is heated by a pulsed laser beam, the beam sweeping the free surface, the wavelength of the beam differing by, at most, plus or minus 15 nm from a central wavelength, the central wavelength being chosen so that the sensitivity of the reflectivity of the structure relative to the insulating layer is zero.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: March 6, 2018
    Assignee: Soitec
    Inventor: Oleg Kononchuk
  • Patent number: 9911641
    Abstract: The invention relates to a process for manufacturing a semiconductor substrate, characterized in that it comprises providing at least one donor semiconductor substrate comprising at least one useful silicon layer; inspecting the donor substrate via an inspecting machine in order to detect whether the useful layer contains emerging cavities of a size larger than or equal to a critical size, said critical size being strictly smaller than 44 nm; and manufacturing a semiconductor substrate comprising at least part of the useful layer of the donor substrate if, considering cavities of a size larger than or equal to the critical size, the density or number of cavities in the useful layer of the donor substrate is lower than or equal to a critical defect density or number.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: March 6, 2018
    Assignee: Soitec
    Inventors: Francois Boedt, Roland Brun, Olivier Ledoux, Eric Butaud
  • Patent number: 9905531
    Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: February 27, 2018
    Assignee: Soitec
    Inventors: Ionut Radu, Marcel Broekaart, Arnaud Castex, Gweltaz Gaudin, Gregory Riou
  • Patent number: 9887124
    Abstract: A process for the manufacture of a composite structure includes the following stages: a) providing a donor substrate comprising a first surface and a support substrate; b) forming a zone of weakening in the donor substrate, the zone of weakening delimiting, with the first surface of the donor substrate, a working layer; c) assembling the support substrate and the donor substrate; d) fracturing the donor substrate along the zone of weakening; and e) thinning the working layer so as to form a thinned working layer. Stage b) is carried out so that the working layer exhibits a thickness profile appropriate for compensating for the nonuniformity in consumption of the working layer during stage e).
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: February 6, 2018
    Assignee: Soitec
    Inventors: Nadia Ben Mohamed, Eric Maze
  • Publication number: 20180024186
    Abstract: The disclosure relates to a device for measuring an electrical characteristic of a substrate comprising a support made of a dielectric material having a bearing surface, the support comprising an electrical test structure having a contact surface flush with the bearing surface of the support, the bearing surface of the support and the contact surface of the electrical test structure being suitable for coming into close contact with a substrate. The measurement device also comprises at least one connection bump contact formed on another surface of the support and electrically linked to the electrical test structure. This disclosure also relates to a system for characterizing a substrate and a method for measuring a characteristic of a substrate employing the measurement device.
    Type: Application
    Filed: January 19, 2016
    Publication date: January 25, 2018
    Applicant: Soitec
    Inventors: Cédric Malaquin, Jean-Pierre Raskin, Eric Desbonnets
  • Patent number: 9875914
    Abstract: A process comprises the following steps: a) provision of a chamber suitable for receiving a plurality of structures, b) circulation of a gas stream in the chamber so that the chamber has a non-oxidizing atmosphere, c) heat treatment of the plurality of structures at a temperature above a threshold value above which the oxygen present in an oxide of a dielectric diffuses through an active layer reacts with semiconductor material of the active layer and produces a volatile material, the process being noteworthy in that the step b) is carried out so that the gas stream has a rate of circulation between the plurality of structures greater than the rate of diffusion of the volatile material into the gas stream.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: January 23, 2018
    Assignee: Soitec
    Inventors: Didier Landru, Oleg Kononchuk, Christophe Gourdel, Carole David, Sebastien Mougel, Xavier Schneider
  • Patent number: 9865786
    Abstract: The disclosure relates to a manufacturing method comprising the formation of elemental LED or photovoltaic structures on a first substrate, each comprising at least one p-type layer, an active zone and an n-type layer, formation of a first planar metal layer on the elemental structures, provision of a transfer substrate comprising a second planar metal layer, assembly of the elemental structures with the transfer substrate by bonding of the first and second metal layers by molecular adhesion at room temperature, and removal of the first substrate.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: January 9, 2018
    Assignee: Soitec
    Inventor: Pascal Guenard
  • Patent number: 9835377
    Abstract: A support device that has a central axis and includes three uprights extending substantially parallel to the central axis, a plurality of series of support members spaced along the central axis, each series of support members comprising three support members adapted to support one wafer of the plurality of wafers and extending in different essentially longitudinal directions transverse to the central axis, each support member being mounted directly on a separate upright, this support device being remarkable in that the directions of the three support members of each series of support members are concurrent at a point on the central axis.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: December 5, 2017
    Assignee: Soitec
    Inventors: Christophe Gourdel, Alexandre Barthelemy
  • Patent number: 9824915
    Abstract: The invention relates to a structure for radiofrequency applications comprising: a monocrystalline substrate, a polycrystalline silicon layer directly on the monocrystalline substrate, and an active layer on the polycrystalline silicon layer intended to receive radiofrequency components. At least a first portion of the polycrystalline silicon layer extending from an interface of the polycrystalline silicon layer with the monocrystalline substrate layer includes carbon and/or nitrogen atoms located at the grain boundaries of the polycrystalline silicon layer at a concentration of between 2% and 20%. A process for manufacturing such a structure includes, during deposition of at least a first portion of such a polycrystalline silicon layer located at the interface with the monocrystalline substrate, depositing carbon and/or atoms in the at least a first portion.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: November 21, 2017
    Assignees: Soitec, Peregrine Semiconductor Corporation
    Inventors: Bich-Yen Nguyen, Christophe Maleville, Sinan Goktepeli, Anthony Mark Miscione, Alain Duvallet
  • Patent number: 9818874
    Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: November 14, 2017
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Mariam Sadaka, Christophe Maleville
  • Patent number: 9812371
    Abstract: The present disclosure relates to a method for reducing metal contamination on a surface of a substrate. The method involves plasma treatment of the surface of the substrate by ion bombardment, wherein a plasma of a supplied gas is generated, and a bombardment energy of the ions in the plasma is controlled by a radio frequency electromagnetic field. The bombardment energy of the ions is higher than a first threshold so as to tear the metal contamination from the surface of the substrate, and the bombardment energy of the ions is lower than a second threshold so as to prevent a surface quality degradation of the surface of the substrate.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: November 7, 2017
    Assignee: Soitec
    Inventor: Thierry Barge
  • Patent number: 9805969
    Abstract: A calibration method for determining temperature set point corrections to be applied to the nominal temperature set points of each of the N heating zones of a heat treatment unit having L substrate locations, includes the following steps: establishing a sensitivity model linking variations of a substrate characteristic at each of M representative locations of the L locations to temperature set point variations applied in each of the N heating zones, the variations respectively reflecting differences with respect to a target characteristic and with respect to the nominal set points; executing the process in the heat treatment unit and on the basis of nominal set points; measuring the substrate characteristic at least at a representative measurement location of each heating zone of the unit to supply M measurements; and determining temperature set point corrections from the sensitivity model, the measurements and the target substrate characteristic.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: October 31, 2017
    Assignee: Soitec
    Inventors: Sebastien Mougel, Didier Masselin
  • Patent number: 9799549
    Abstract: The disclosure relates to a process for manufacturing a composite structure, the process comprising the following steps: a) providing a donor substrate and a carrier substrate; b) forming a dielectric layer; c) forming a covering layer; d) forming a weakened zone in the donor substrate; e) joining the carrier substrate and the donor substrate via a contact surface having an outline; f) fracturing the donor substrate via the weakened zone, steps b) and e) being executed so that the outline is inscribed in the outline, and step c) being executed so that the covering layer covers the peripheral surface of the dielectric layer.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: October 24, 2017
    Assignee: Soitec
    Inventors: Sebastien Kerdiles, Guillaume Chabanne, Francois Boedt, Aurelia Pierret, Xavier Schneider, Didier Landru
  • Patent number: 9793360
    Abstract: Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: October 17, 2017
    Assignee: Soitec
    Inventor: Chantal Arena
  • Patent number: 9768057
    Abstract: A method for transferring a layer from a single-crystal substrate, called a donor substrate, onto a receiver substrate, includes supplying the single-crystal donor substrate, the substrate having a notch oriented in a first direction of the crystal and a weakness region bounding the layer to be transferred, bonding of the single-crystal donor substrate onto the receiver substrate, the main surface of the donor substrate opposite to the weakness region with respect to the layer to be transferred being at the bonding interface, and detachment of the donor substrate along the weakness region. In the method, the donor substrate has, on the main surface bonded to the receiver substrate, an array of atomic steps extending essentially in a second direction of the crystal different from the first direction.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: September 19, 2017
    Assignee: Soitec
    Inventors: Ludovic Ecarnot, Nicolas Daval, Nadia Ben Mohamed, Francois Boedt, Carole David, Isabelle Guerin
  • Patent number: 9759546
    Abstract: The invention relates to a method for measuring thickness variations in a layer of a multilayer semiconductor structure, characterized in that it comprises: acquiring, via an image acquisition system, at least one image of the surface of the structure, the image being obtained by reflecting an almost monochromatic light flux from the surface of the structure; and processing the at least one acquired image in order to determine, from variations in the intensity of the light reflected from the surface, variations in the thickness of the layer to be measured, and in that the wavelength of the almost monochromatic light flux is chosen to correspond to a minimum of the sensitivity of the reflectivity of a layer of the structure other than the layer the thickness variations of which must be measured, the sensitivity of the reflectivity of a layer being equal to the ratio of: the difference between the reflectivities of two multilayer structures for which the layer in question has a given thickness difference; to th
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: September 12, 2017
    Assignees: Soitec, STMICROELECTRONICS (Crolles 2) SAS
    Inventors: Oleg Kononchuk, Didier Dutartre
  • Patent number: 9728458
    Abstract: Methods of fabricating a semiconductor structure include bonding a carrier wafer over a substrate, removing at least a portion of the substrate, transmitting laser radiation through the carrier wafer and weakening a bond between the substrate and the carrier wafer, and separating the carrier wafer from the substrate. Other methods include forming circuits over a substrate, forming trenches in the substrate to define unsingulated semiconductor dies, bonding a carrier substrate over the unsingulated semiconductor dies, transmitting laser radiation through the carrier substrate and weakening a bond between the unsingulated semiconductor dies and the carrier substrate, and separating the carrier substrate from the unsingulated semiconductor dies. Some methods include thinning at least a portion of the substrate, leaving the plurality of unsingulated semiconductor dies bonded to the carrier substrate.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: August 8, 2017
    Assignee: Soitec
    Inventors: Mariam Sadaka, Bernard Aspar, Chrystelle Lagahe Blanchard
  • Patent number: 9718261
    Abstract: A method for assembling two substrates by molecular adhesion comprises: a first step (a) of putting first and second substrates in close contact in order to form an assembly having an assembly interface; a second step (b) of reinforcing the degree of adhesion of the assembly beyond a threshold adhesion value at which water is no longer able to diffuse along the assembly interface. The method also comprises a step (c) of anhydrous treatment of the first and second substrates in a treatment atmosphere having a dew point below ?10° C., and control of the dew point of a working atmosphere to which the first and second substrates are exposed from the anhydrous treatment step (c) until the end of the second step (b) so as to limit or prevent the appearance of bonding defects at the assembly interface.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: August 1, 2017
    Assignees: SOITEC, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Didier Landru, Capucine Delage, Franck Fournel, Elodie Beche