Abstract: Disclosed herein is an low power output stage coupled between a supply node and a ground node, configured to drive an output, and controlled by first, second, and third control nodes. A current sinking circuit controlled by an input signal and configured to sink current from the first and second control nodes when the input signal transitions to a first logic level, thereby resulting in decoupling of the output stage from the ground node and sourcing of current to the output by the output stage. When the input signal transitions to a second logic level different than the first logic level, the current sinking circuit sinks current from a third control node, thereby resulting in decoupling of the output stage from the supply node and sinking of current from the output by the output stage.

Abstract: A video and/or audio decoder provided with a first terminal for supplying an analog audio and/or video signal, including: a first circuit capable of supplying a digital signal which is an image of said analog signal; a digital-to-analog converter capable of receiving as an input said digital signal; an amplifier coupling a second output terminal of the digital-to-analog converter to the first terminal; and a second circuit capable of comparing a signal representative of the voltage or current level on the first terminal with a reference signal, and of deducing therefrom whether the first terminal is connected or not to an analog input terminal of a video signal display and/or audio signal playing device.

Abstract: A transistor includes a quasi-intrinsic region of a first conductivity type that is covered with an insulated gate. The quasi-intrinsic region extends between two first doped regions of a second conductivity type. A main electrode is provided on each of the two first doped regions. A second doped region of a second conductivity type is position in contact with the quasi-intrinsic region, but is electrically and physically separated by a distance from the two first doped regions. A control electrode is provided on the second doped region.

Abstract: Disclosed herein is a mirror controller for an oscillating mirror. The mirror controller includes a processor configured to receive a mirror sense signal from the oscillating mirror and to determine a phase error between the mirror sense signal and a mirror drive signal. The processor determines the phase error by sampling the mirror sense signal at a first time, sampling the mirror sense signal at a second time at which the mirror sense signal is expected to be equal to the mirror sense signal as sampled at the first time, and generating the phase error as a function of a difference between the sample of the mirror sense signal at the second time and the sample of the mirror sense signal at the first time.

Abstract: A method of foreign matter rejection for multi-touch capacitive touch screens includes performing touch detection in both self-capacitance mode and mutual capacitance mode. By combining information from both modes, a distinction is identified between wanted touches, such as by a finger or stylus, and unwanted touches such as by foreign matter.

Abstract: An image sensor manufacturing method includes forming a cavity in a first plate and mounting an active layer including both image sensing components and logic components to the first plate. The active layer is pressed against the first plate in a manner such that the image sensing components in the active layer are located on walls of the cavity and the logic components in the active layer are located outside of the cavity.

Abstract: An electronic device includes a base substrate, and a plurality of battery substrates constructed from mica and being attached to the base substrate. An aggregate area of the base substrate is greater than an aggregate area of the plurality of battery substrates. The electronic device also includes a plurality of active battery layers, each active battery layer being attached to a different respective battery substrate, with each active battery layer having a smaller area than its corresponding battery substrate. A film is disposed over the plurality of active battery layers and sized such that the film extends beyond each active battery layer to contact each battery substrate, and such that the film extends beyond each battery substrate to contact the base substrate.

Abstract: One or more embodiments are directed to a microfluidic assembly that includes an interconnect substrate coupled to a microfluidic die. In one embodiment, the microfluidic die includes a ledge with a plurality of bond pads. The microfluidic assembly further includes an interconnect substrate having an end resting on the ledge proximate the bond pads. In another embodiment, the interconnect substrate abuts a side surface of the ledge or is located proximate the ledge. Conductive elements couple the microfluidic die to contacts of the interconnect substrate. Encapsulant is located over the conductive elements, the bond pads, the contacts.

Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.

Abstract: An activity tracking device, such as a step-counting device includes an interface configured to receive one or more acceleration signals and signal processing circuitry. The signal processing circuitry generates an indication of condition of an accelerometer, such as a body position of the accelerometer, based on one or more accelerometer signals, generates an event signal, such as an event flag, based on one or more accelerometer signals and the indication of the condition of the accelerometer, and generates an activity signal, such as step flag based on the event signal, the indication of the condition of the accelerometer and one or more acceleration signals. The signal processing circuitry may generate a noise signal based on one or more acceleration signals and generate the activity signal based on the noise signal.

Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

Abstract: An integrated circuit includes a number of components disposed at a surface of a semiconductor body and an interconnect region connecting the components into a functional circuit. A metallic shield is also produced in the interconnect region. A configurable stage is configurable to operate in a receiving antenna configuration or in a detection configuration during which the integrated circuit is configured to detect a presence of an external electromagnetic radiation representative of an attack by injection of faults.

Abstract: An E/O phase modulator may include a waveguide having an insulating substrate, a single-crystal silicon strip and a polysilicon strip of a same thickness and doped with opposite conductivity types above the insulating substrate, and an insulating interface layer between the single-crystal silicon strip and polysilicon strip. Each of the single-crystal silicon strip and polysilicon strip may be laterally continued by a respective extension, and a respective electrical contact coupled to each extension.

Abstract: A method can be used for transmission of at least one packet of at least one bit over a serial link capable of taking two different states respectively associated with the two possible logical values of the at least one transmitted bit. Starting from a transmission start time of the at least one bit and up to the expiration of a first portion of a bit time associated with the at least one bit, the link is placed in one of its states depending on the logical value of the at least one bit. Upon the expiration of the first portion of this bit time, a first additional transition is generated over the link so as to place the link in its other state up to the expiration of the bit time.

Abstract: An integrated circuit includes an output terminal a first input terminal is configured to receive a signal proportional to a voltage between first and second terminals of the primary winding, and a second input terminal is configured to receive a signal proportional to a current flowing through the primary winding. A quasi-resonant (QR) circuit has a first input coupled to the first terminal, and a second input coupled to an output of an oscillator circuit. A selector circuit has a first input coupled to the output of the oscillator circuit, a second input coupled to an output of the QR circuit, and a select input. An output control circuit includes a first input coupled to the second input terminal, a second input coupled to an output of the selector circuit, and an output coupled to a control terminal of the switching transistor.

Abstract: An integrated circuit includes at least two identical, synchronous and independent oscillator circuits that are coupled one to one in parallel with each other at homologous oscillating nodes of the respective oscillator circuits. The coupling in parallel is made using at least one coupling track that is configured so as to not introduce any phase shift or to introduce a very small phase shift.

Abstract: An RFID transponder includes a coding and modulation unit that generates a transmission signal by modulating an oscillator signal with an encoded bit signal. During a first and a second time segment, the encoded bit signal assumes a first and a second logic level, respectively. The transmission signal includes a first signal pulse having a first phase within the first time segment and a second signal pulse having a second phase that is shifted with respect to the first phase by a predefined phase difference within the second time segment. The transmission signal is paused for a pause period between the first and the second signal pulse. The pause period is shorter than a mean value of a period of the first time segment and a period of the second time segment.

Abstract: A device for measuring impedance of biological tissue may include electrodes and a voltage-to-current converter coupled to the electrodes to drive an alternating current (AC) through the tissue and sense an AC voltage. The converter may include an amplifier having first and second inputs and an output, a first voltage divider coupled to the first input, a second voltage divider coupled to the second input, a filter capacitor coupled between the output and the second voltage divider, a current limiting resistor coupled between the second input the second voltage divider, and a bypass capacitor coupled to the second input of the amplifier and in parallel with the resistor. A single-ended amplitude modulation (AM) demodulator may demodulate the AC voltage and generate a corresponding baseband voltage representing the impedance. The device may also include an output circuit to generate output signals representative of DC and AC components of the baseband voltage.

Abstract: A global shutter image sensor of a back-illuminated type includes a semiconductor substrate and pixels. Each pixel includes a photosensitive area, a storage area, a readout area and areas for transferring charges between these different areas. The image sensor includes, for each pixel, a protector extending at least partly into the substrate from the back of the substrate to ensure that the storage area is protected against back illumination.

Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.