Abstract: An electro-optical phase modulator includes a waveguide made from a stack of strips. The stack includes a first strip made of a doped semiconductor material of a first conductivity type, a second strip made of a conductive material or of a doped semiconductor material of a second conductivity type, and a third strip made of a doped semiconductor material of the first conductivity type. The second strip is separated from the first strip by a first interface layer made of a dielectric material, and the third strip is separated from the second strip by a second interface layer made of a dielectric material.

Abstract: Disclosed herein is a touch screen controller operable with a touch screen having force lines and sense lines. The touch screen controller includes drive circuitry driving the force lines with a force signal in a touch data sensing mode and not driving the force lines in a noise sensing mode. Sense circuitry senses data at the sense lines in the touch data sensing mode and the noise sensing mode. Processing circuitry samples the data, multiplies the data by a sine multiplier to produce imaginary data, sums the imaginary data, multiplies the data by a cosine multiplier to produce real data, sums the real data, and determines magnitude values of the data as a function of the imaginary data and the real data.

Abstract: A DC-DC converter includes a power oscillator connected to a first transformer winding, and a channel conveying a data stream through galvanic isolation by power signal modulation. A rectifier rectifies the power signal to produce a DC voltage. A comparator produces an error signal from the DC voltage and a reference voltage. An analog-to-digital converter converts the error signal to a digital power control value. A multiplexer multiplexes the digital power control value with the data stream to obtain a multiplexed bitstream. A transmitter driven by the multiplexed bitstream performs amplitude modulation of the power signal at a second transformer winding. A receiver connected to the first winding demodulates the amplitude modulated power signal. A demultiplexer demultiplexes the data stream and the digital power control value. A digital-to-analog converter converts the digital power control value to an analog control signal for the power oscillator.

Abstract: An AC/DC converter includes a first terminal and a second terminal to receive an AC voltage and a third terminal and a fourth terminal to deliver a DC voltage. A rectifying bridge is provided in the converter. A controllable switching or rectifying element has a control terminal configured to receive a control current. A first switch is coupled between a supply voltage and the control terminal to inject the control current. A second switch is coupled between the control terminal and a reference voltage to extract the control current. The first and second switches are selectively actuated by a control circuit.

Abstract: A micromechanical mirror structure includes a mirror element designed to reflect an incident light radiation and a protective structure arranged over the mirror element to provide mechanical protection for the mirror element and to increase the reflectivity of the mirror element with respect to the incident light radiation. The protective structure has a first protective layer and a second protective layer which are stacked on the mirror element. The second protective layer is arranged on the first protective layer and the first protective layer is arranged on the mirror element. The layers include a respective dielectric material and having respective refractive indexes that jointly increase the reflectivity of the mirror element in a range of wavelengths of interest.

Abstract: A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.

Abstract: One or more embodiments are directed to system in package (SiP) for optical devices, such as proximity sensing or optical ranging devices. One embodiment is directed to an optical sensor package that includes a substrate, a sensor die coupled to the substrate, a light-emitting device coupled to the substrate, and a cap. The cap is positioned around side surfaces of the sensor die and covers at least a portion of the substrate. The cap includes first and second sidewalls, an inner wall having first and second side surfaces and a mounting surface, and a cover in contact with the first and second sidewalls and the inner wall. The first and second side surfaces are transverse to the mounting surface, and the inner wall includes an opening extending into the inner wall from the mounting surface. A first adhesive material is provided on the sensor die and at least partially within the opening, and secures the inner wall to the sensor die.

Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.

Abstract: A pixel includes a semiconductor layer with a charge accumulation layer extending in the semiconductor layer. A transistor has a read region penetrating into said semiconductor layer down to a first depth. An insulating wall penetrates into the semiconductor layer from an upper surface and containing an insulated conductor connected to a node of application of a potential. The insulating wall includes at least a portion provided with a deep insulating plug penetrating into the insulated conductor down to a second depth greater than the first depth. A continuous portion of the insulating wall laterally delimits, at least partially, a charge accumulation area and includes a wall portion with the deep insulating plug at least partially laterally delimiting the read region of the transistor.

Abstract: Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.

Abstract: A MEMS sensor, in particular a microphone, of a piezoelectric type, formed in a membrane of semiconductor material accommodating a compliant portion, which extends from a first surface to a second surface of the membrane. The compliant portion has a Young's modulus lower than the rest of the membrane. A sensitive region having piezoelectric material extends on the first surface, over the compliant portion and is fixed at its ends to the membrane on opposite sides of the compliant portion. A third area of the membrane, arranged between the compliant portion and the second surface, forms a hinge element.

Abstract: A method of manufacturing a magnetic-field sensor includes forming an insulating layer on a first surface of a substrate. First and second magnetoresistors are formed at different above the first surface of the substrate and are spaced apart from the first surface by different distances. The first and second magnetoresistors have respective main axes of magnetization transverse to one another, and respective secondary axes of magnetization transverse to one another. The method further includes forming a first magnetic-field generator configured to generate a first magnetic field having field lines along the main axis of magnetization of the first magnetoresistor, and forming a second magnetic-field generator configured to generate a second magnetic field having field lines along the main axis of magnetization of the second magnetoresistor.

Abstract: An embodiment method of detecting an arc fault includes communicating a power line signal, including a communication signal modulated on an alternating current power signal, over a power line. The communication signal is communicated according to a power line network protocol. A power spectrum of the communication signal includes a first frequency band and a second frequency band different from the first frequency band. In accordance with the power line network protocol, a power of the communication signal in the first frequency band is attenuated in comparison to the power of the communication signal in the second frequency band. The method further includes performing arc fault detection on the spectral portions of the power line signal that are within the first frequency band.

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

Abstract: A base carries a first chip and a second chip oriented differently with respect to the base and packaged in a package. Each chip integrates an antenna and a magnetic via. A magnetic coupling path connects the chips, forming a magnetic circuit that enables transfer of signals and power between the chips even if the magnetic path is interrupted, and is formed by a first stretch coupled between the first magnetic-coupling element of the first chip and the first magnetic-coupling element of the second chip, and a second stretch coupled between the second magnetic-coupling element of the first chip and the second magnetic-coupling element of the second chip. The first stretch has a parallel portion extending parallel to the faces of the base. The first and second stretches have respective transverse portions extending on the main surfaces of the second chip, transverse to the parallel portion.

Abstract: A level shifting circuit receives a first input signal and complement of the first input signal as inputs and generates a level shifted first output signal and complement of the first output signal as outputs. The level shifting circuit includes a number of transistors that support body biasing. One set of body bias signals applied to certain ones of those transistors is generated as a function of the logical combination of the first input signal and the first output signal. Another set of body bias signals applied to certain other ones of those transistors is generated as a function of the logical combination of the complement of the first input signal and the complement of the first output signal. The conditional body bias applied to the transistors of the level shifting circuit makes the circuit operational for level shift at very low supply voltage levels.

Abstract: A radio-frequency identification (RFID) device includes an RFID block configured to support RFID communication; a memory having a storage area configured to store a list of pulse width modulation (PWM) parameters; a PWM circuit configured to generate a PWM signal based on a PWM parameter received by the PWM circuit; and a configuration and control (CC) circuit coupled to the RFID block, the memory, and the PWM circuit, where the RFID block, the PWM circuit, the CC circuit, and the memory form part of an RFID tag, where the CC circuit is configured to, in an automatic playback mode: sequentially read the list of PWM parameters from a beginning of the list of PWM parameters; and sequentially send the list of PWM parameters to the PWM circuit.

Abstract: A method of protecting a modular calculation on a first number and a second number, executed by an electronic circuit, including the steps of: combining the second number with a third number to obtain a fourth number; executing the modular calculation on the first and fourth numbers, the result being contained in a first register or memory location; initializing a second register or memory location to the value of the first register or to one; and successively, for each bit at state 1 of the third number: if the corresponding bit of the fourth number is at state 1, multiplying the content of the second register or memory location by the inverse of the first number and placing the result in the first register or memory location, if the corresponding bit of the fourth number is at state 0, multiplying the content of the second register or memory location by the first number and placing the result in the first register or memory location.

Abstract: A voltage or current generator has a configurable temperature coefficient and includes a first voltage generator that generates a first voltage having a first negative temperature coefficient. A second voltage generator generates a second voltage having a second negative temperature coefficient different to the first negative temperature coefficient. A circuit generates an output level based on the difference between the first voltage scaled by a first scale factor and the second voltage scaled by a second scale factor.